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ir3: Make branch conditions non-SSA
In particular, make sure they have a physreg assigned. This was the last place after RA where SSA registers were created, which won't work with the new post-RA delay calculation that relies on the physreg. Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9842>
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c0823a2d31
2 changed files with 14 additions and 8 deletions
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@ -627,12 +627,16 @@ block_sched(struct ir3 *ir)
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/* create "else" branch first (since "then" block should
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* frequently/always end up being a fall-thru):
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*/
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br = ir3_B(block, block->condition, 0);
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br = ir3_instr_create(block, OPC_B, 2);
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ir3_reg_create(br, INVALID_REG, IR3_REG_DEST);
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ir3_reg_create(br, regid(REG_P0, 0), 0)->def = block->condition->regs[0];
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br->cat0.inv1 = true;
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br->cat0.target = block->successors[1];
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/* "then" branch: */
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br = ir3_B(block, block->condition, 0);
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br = ir3_instr_create(block, OPC_B, 2);
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ir3_reg_create(br, INVALID_REG, IR3_REG_DEST);
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ir3_reg_create(br, regid(REG_P0, 0), 0)->def = block->condition->regs[0];
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br->cat0.target = block->successors[0];
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} else if (block->successors[0]) {
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@ -331,16 +331,18 @@ print_instr(struct ir3_instruction *instr, int lvl)
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printf(".%u", instr->cat0.idx);
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}
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if (brinfo[instr->cat0.brtype].nsrc >= 1) {
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printf(" %sp0.%c ("SYN_SSA("ssa_%u")"),",
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printf(" %sp0.%c (",
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instr->cat0.inv1 ? "!" : "",
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"xyzw"[instr->cat0.comp1 & 0x3],
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instr->regs[1]->def->instr->serialno);
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"xyzw"[instr->cat0.comp1 & 0x3]);
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print_reg_name(instr, instr->regs[1]);
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printf("), ");
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}
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if (brinfo[instr->cat0.brtype].nsrc >= 2) {
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printf(" %sp0.%c ("SYN_SSA("ssa_%u")"),",
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printf(" %sp0.%c (",
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instr->cat0.inv2 ? "!" : "",
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"xyzw"[instr->cat0.comp2 & 0x3],
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instr->regs[2]->def->instr->serialno);
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"xyzw"[instr->cat0.comp2 & 0x3]);
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print_reg_name(instr, instr->regs[2]);
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printf("), ");
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}
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}
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printf(" target=block%u", block_id(instr->cat0.target));
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