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brw: Refactor clip/cull distance mask setting into a helper

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This was copy pasted between 4 different stages.

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37784>
This commit is contained in:
Kenneth Graunke 2025-10-09 02:16:49 -07:00
parent b3c511592a
commit bf76e86bc8
5 changed files with 25 additions and 47 deletions
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12
src/intel/compiler/brw/brw_compile_gs.cpp
View file

@ -180,18 +180,6 @@ brw_compile_gs(const struct brw_compiler *compiler,
params->base.archiver, debug_enabled,
key->base.robust_flags);
const bool has_clip_cull_dist =
nir->info.outputs_written & (VARYING_BIT_CLIP_DIST0 |
VARYING_BIT_CLIP_DIST1 |
VARYING_BIT_CULL_DIST0 |
VARYING_BIT_CULL_DIST1);
prog_data->base.clip_distance_mask = has_clip_cull_dist ?
((1 << nir->info.clip_distance_array_size) - 1) : 0;
prog_data->base.cull_distance_mask =
(has_clip_cull_dist ?
((1 << nir->info.cull_distance_array_size) - 1) : 0) <<
nir->info.clip_distance_array_size;
prog_data->include_primitive_id =
BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_PRIMITIVE_ID);

11
src/intel/compiler/brw/brw_compile_mesh.cpp
View file

@ -1192,17 +1192,6 @@ brw_compile_mesh(const struct brw_compiler *compiler,
prog_data->base.local_size[1] = nir->info.workgroup_size[1];
prog_data->base.local_size[2] = nir->info.workgroup_size[2];
const bool has_clip_cull_dist =
nir->info.outputs_written & (VARYING_BIT_CLIP_DIST0 |
VARYING_BIT_CLIP_DIST1 |
VARYING_BIT_CULL_DIST0 |
VARYING_BIT_CULL_DIST1);
prog_data->clip_distance_mask = has_clip_cull_dist ?
(1 << nir->info.clip_distance_array_size) - 1 : 0;
prog_data->cull_distance_mask =
(has_clip_cull_dist ?
((1 << nir->info.cull_distance_array_size) - 1) : 0) <<
nir->info.clip_distance_array_size;
prog_data->primitive_type = nir->info.mesh.primitive_type;
/* Apply this workaround before trying to pack indices because this can

12
src/intel/compiler/brw/brw_compile_tes.cpp
View file

@ -113,18 +113,6 @@ brw_compile_tes(const struct brw_compiler *compiler,
return NULL;
}
const bool has_clip_cull_dist =
nir->info.outputs_written & (VARYING_BIT_CLIP_DIST0 |
VARYING_BIT_CLIP_DIST1 |
VARYING_BIT_CULL_DIST0 |
VARYING_BIT_CULL_DIST1);
prog_data->base.clip_distance_mask = has_clip_cull_dist ?
((1 << nir->info.clip_distance_array_size) - 1) : 0;
prog_data->base.cull_distance_mask =
(has_clip_cull_dist ?
((1 << nir->info.cull_distance_array_size) - 1) : 0) <<
nir->info.clip_distance_array_size;
prog_data->include_primitive_id =
BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_PRIMITIVE_ID);

12
src/intel/compiler/brw/brw_compile_vs.cpp
View file

@ -283,18 +283,6 @@ brw_compile_vs(const struct brw_compiler *compiler,
params->base.archiver, debug_enabled,
key->base.robust_flags);
const bool has_clip_cull_dist =
nir->info.outputs_written & (VARYING_BIT_CLIP_DIST0 |
VARYING_BIT_CLIP_DIST1 |
VARYING_BIT_CULL_DIST0 |
VARYING_BIT_CULL_DIST1);
prog_data->base.clip_distance_mask = has_clip_cull_dist ?
((1 << nir->info.clip_distance_array_size) - 1) : 0;
prog_data->base.cull_distance_mask =
(has_clip_cull_dist ?
((1 << nir->info.cull_distance_array_size) - 1) : 0) <<
nir->info.clip_distance_array_size;
unsigned nr_attribute_slots = util_bitcount64(prog_data->inputs_read);
/* gl_VertexID and gl_InstanceID are system values, but arrive via an
* incoming vertex attribute. So, add an extra slot.

25
src/intel/compiler/brw/brw_from_nir.cpp
View file

@ -7924,6 +7924,29 @@ brw_test_dispatch_packing(const brw_builder &bld)
}
}
static void
set_clip_cull_distance_masks(brw_shader &s)
{
const shader_info &info = s.nir->info;
if (info.stage >= MESA_SHADER_FRAGMENT && info.stage != MESA_SHADER_MESH)
return;
struct brw_vue_prog_data *prog_data = brw_vue_prog_data(s.prog_data);
if (info.outputs_written &
(VARYING_BIT_CLIP_DIST0 | VARYING_BIT_CLIP_DIST1 |
VARYING_BIT_CULL_DIST0 | VARYING_BIT_CULL_DIST1)) {
prog_data->clip_distance_mask =
((1 << info.clip_distance_array_size) - 1);
prog_data->cull_distance_mask =
((1 << info.cull_distance_array_size) - 1)
<< info.clip_distance_array_size;
}
}
void
brw_from_nir(brw_shader *s)
{
@ -7941,6 +7964,8 @@ brw_from_nir(brw_shader *s)
if (ENABLE_TEST_DISPATCH_PACKING)
brw_test_dispatch_packing(ntb.bld);
set_clip_cull_distance_masks(*s);
emit_shader_float_controls_execution_mode(ntb);
/* emit the arrays used for inputs and outputs - load/store intrinsics will