diff --git a/src/intel/compiler/brw/brw_compile_gs.cpp b/src/intel/compiler/brw/brw_compile_gs.cpp index 655a683fa1d..366f522fc01 100644 --- a/src/intel/compiler/brw/brw_compile_gs.cpp +++ b/src/intel/compiler/brw/brw_compile_gs.cpp @@ -180,18 +180,6 @@ brw_compile_gs(const struct brw_compiler *compiler, params->base.archiver, debug_enabled, key->base.robust_flags); - const bool has_clip_cull_dist = - nir->info.outputs_written & (VARYING_BIT_CLIP_DIST0 | - VARYING_BIT_CLIP_DIST1 | - VARYING_BIT_CULL_DIST0 | - VARYING_BIT_CULL_DIST1); - prog_data->base.clip_distance_mask = has_clip_cull_dist ? - ((1 << nir->info.clip_distance_array_size) - 1) : 0; - prog_data->base.cull_distance_mask = - (has_clip_cull_dist ? - ((1 << nir->info.cull_distance_array_size) - 1) : 0) << - nir->info.clip_distance_array_size; - prog_data->include_primitive_id = BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_PRIMITIVE_ID); diff --git a/src/intel/compiler/brw/brw_compile_mesh.cpp b/src/intel/compiler/brw/brw_compile_mesh.cpp index 829ba4260f3..f9f6c79d9a3 100644 --- a/src/intel/compiler/brw/brw_compile_mesh.cpp +++ b/src/intel/compiler/brw/brw_compile_mesh.cpp @@ -1192,17 +1192,6 @@ brw_compile_mesh(const struct brw_compiler *compiler, prog_data->base.local_size[1] = nir->info.workgroup_size[1]; prog_data->base.local_size[2] = nir->info.workgroup_size[2]; - const bool has_clip_cull_dist = - nir->info.outputs_written & (VARYING_BIT_CLIP_DIST0 | - VARYING_BIT_CLIP_DIST1 | - VARYING_BIT_CULL_DIST0 | - VARYING_BIT_CULL_DIST1); - prog_data->clip_distance_mask = has_clip_cull_dist ? - (1 << nir->info.clip_distance_array_size) - 1 : 0; - prog_data->cull_distance_mask = - (has_clip_cull_dist ? - ((1 << nir->info.cull_distance_array_size) - 1) : 0) << - nir->info.clip_distance_array_size; prog_data->primitive_type = nir->info.mesh.primitive_type; /* Apply this workaround before trying to pack indices because this can diff --git a/src/intel/compiler/brw/brw_compile_tes.cpp b/src/intel/compiler/brw/brw_compile_tes.cpp index c26a293f6f3..56c79e5cddf 100644 --- a/src/intel/compiler/brw/brw_compile_tes.cpp +++ b/src/intel/compiler/brw/brw_compile_tes.cpp @@ -113,18 +113,6 @@ brw_compile_tes(const struct brw_compiler *compiler, return NULL; } - const bool has_clip_cull_dist = - nir->info.outputs_written & (VARYING_BIT_CLIP_DIST0 | - VARYING_BIT_CLIP_DIST1 | - VARYING_BIT_CULL_DIST0 | - VARYING_BIT_CULL_DIST1); - prog_data->base.clip_distance_mask = has_clip_cull_dist ? - ((1 << nir->info.clip_distance_array_size) - 1) : 0; - prog_data->base.cull_distance_mask = - (has_clip_cull_dist ? - ((1 << nir->info.cull_distance_array_size) - 1) : 0) << - nir->info.clip_distance_array_size; - prog_data->include_primitive_id = BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_PRIMITIVE_ID); diff --git a/src/intel/compiler/brw/brw_compile_vs.cpp b/src/intel/compiler/brw/brw_compile_vs.cpp index 58b54d39d34..ab219d8a77a 100644 --- a/src/intel/compiler/brw/brw_compile_vs.cpp +++ b/src/intel/compiler/brw/brw_compile_vs.cpp @@ -283,18 +283,6 @@ brw_compile_vs(const struct brw_compiler *compiler, params->base.archiver, debug_enabled, key->base.robust_flags); - const bool has_clip_cull_dist = - nir->info.outputs_written & (VARYING_BIT_CLIP_DIST0 | - VARYING_BIT_CLIP_DIST1 | - VARYING_BIT_CULL_DIST0 | - VARYING_BIT_CULL_DIST1); - prog_data->base.clip_distance_mask = has_clip_cull_dist ? - ((1 << nir->info.clip_distance_array_size) - 1) : 0; - prog_data->base.cull_distance_mask = - (has_clip_cull_dist ? - ((1 << nir->info.cull_distance_array_size) - 1) : 0) << - nir->info.clip_distance_array_size; - unsigned nr_attribute_slots = util_bitcount64(prog_data->inputs_read); /* gl_VertexID and gl_InstanceID are system values, but arrive via an * incoming vertex attribute. So, add an extra slot. diff --git a/src/intel/compiler/brw/brw_from_nir.cpp b/src/intel/compiler/brw/brw_from_nir.cpp index cc225f268c6..18e8ec27305 100644 --- a/src/intel/compiler/brw/brw_from_nir.cpp +++ b/src/intel/compiler/brw/brw_from_nir.cpp @@ -7924,6 +7924,29 @@ brw_test_dispatch_packing(const brw_builder &bld) } } +static void +set_clip_cull_distance_masks(brw_shader &s) +{ + const shader_info &info = s.nir->info; + + if (info.stage >= MESA_SHADER_FRAGMENT && info.stage != MESA_SHADER_MESH) + return; + + struct brw_vue_prog_data *prog_data = brw_vue_prog_data(s.prog_data); + + if (info.outputs_written & + (VARYING_BIT_CLIP_DIST0 | VARYING_BIT_CLIP_DIST1 | + VARYING_BIT_CULL_DIST0 | VARYING_BIT_CULL_DIST1)) { + + prog_data->clip_distance_mask = + ((1 << info.clip_distance_array_size) - 1); + + prog_data->cull_distance_mask = + ((1 << info.cull_distance_array_size) - 1) + << info.clip_distance_array_size; + } +} + void brw_from_nir(brw_shader *s) { @@ -7941,6 +7964,8 @@ brw_from_nir(brw_shader *s) if (ENABLE_TEST_DISPATCH_PACKING) brw_test_dispatch_packing(ntb.bld); + set_clip_cull_distance_masks(*s); + emit_shader_float_controls_execution_mode(ntb); /* emit the arrays used for inputs and outputs - load/store intrinsics will