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anv: flush render caches on first pipeline select

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Given a situation like this :
  - CB_A: begin, renderDepthA, end
  - CB_B: begin, computeA, barrier (depth), computeB, end

The depth cache is not being flushed between renderDepthA & computeB
because :
  - it's not flushed at the end of CB_A (it's not required)
  - when CB_B starts, we're still on GFX pipeline mode but do not
    flush render caches because pipeline mode is unknown
  - when barrier is CB_B is executed, we're already in compute
    pipeline mode and HW cannot flush depth.

The fix is to flush RT/depth cached when switching from unknown
pipeline mode any pipeline mode.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: e6dae6ef5f ("vulkan: Optimize implicit end_subpass barrier")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/14816
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Tested-by: David Gow <david@davidgow.net>
(cherry picked from commit 888ac904a3)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39969>
This commit is contained in:
Lionel Landwerlin 2026-02-11 13:59:36 +02:00 • committed by Dylan Baker
parent 3cc3c5a577
commit becf4f34ec
2 changed files with 6 additions and 2 deletions
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2
.pick_status.json
View file

@ -484,7 +484,7 @@
"description": "anv: flush render caches on first pipeline select",
"nominated": true,
"nomination_type": 2,
"resolution": 0,
"resolution": 1,
"main_sha": null,
"because_sha": "e6dae6ef5fc134f9ed5dd93b1a462084bc3aadfd",
"notes": null

6
src/intel/vulkan/genX_cmd_buffer.c
View file

@ -4867,7 +4867,11 @@ genX(flush_pipeline_select)(struct anv_cmd_buffer *cmd_buffer,
*/
bits |= ANV_PIPE_CS_STALL_BIT | ANV_PIPE_HDC_PIPELINE_FLUSH_BIT;
if (cmd_buffer->state.current_pipeline == _3D) {
if (cmd_buffer->state.current_pipeline == UINT32_MAX) {
bits |= ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT |
ANV_PIPE_DEPTH_CACHE_FLUSH_BIT |
ANV_PIPE_UNTYPED_DATAPORT_CACHE_FLUSH_BIT;
} else if (cmd_buffer->state.current_pipeline == _3D) {
bits |= ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT |
ANV_PIPE_DEPTH_CACHE_FLUSH_BIT;
} else {