From becf4f34ec346f80a22bfe1a268e11773103dc8c Mon Sep 17 00:00:00 2001 From: Lionel Landwerlin Date: Wed, 11 Feb 2026 13:59:36 +0200 Subject: [PATCH] anv: flush render caches on first pipeline select MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Given a situation like this : - CB_A: begin, renderDepthA, end - CB_B: begin, computeA, barrier (depth), computeB, end The depth cache is not being flushed between renderDepthA & computeB because : - it's not flushed at the end of CB_A (it's not required) - when CB_B starts, we're still on GFX pipeline mode but do not flush render caches because pipeline mode is unknown - when barrier is CB_B is executed, we're already in compute pipeline mode and HW cannot flush depth. The fix is to flush RT/depth cached when switching from unknown pipeline mode any pipeline mode. Signed-off-by: Lionel Landwerlin Fixes: e6dae6ef5fc ("vulkan: Optimize implicit end_subpass barrier") Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/14816 Reviewed-by: José Roberto de Souza Tested-by: David Gow (cherry picked from commit 888ac904a34da1e467a3943d555336edda444ada) Part-of: --- .pick_status.json | 2 +- src/intel/vulkan/genX_cmd_buffer.c | 6 +++++- 2 files changed, 6 insertions(+), 2 deletions(-) diff --git a/.pick_status.json b/.pick_status.json index 4a44fed47b5..b8b69a9c687 100644 --- a/.pick_status.json +++ b/.pick_status.json @@ -484,7 +484,7 @@ "description": "anv: flush render caches on first pipeline select", "nominated": true, "nomination_type": 2, - "resolution": 0, + "resolution": 1, "main_sha": null, "because_sha": "e6dae6ef5fc134f9ed5dd93b1a462084bc3aadfd", "notes": null diff --git a/src/intel/vulkan/genX_cmd_buffer.c b/src/intel/vulkan/genX_cmd_buffer.c index 75524290efb..ca89bef93f0 100644 --- a/src/intel/vulkan/genX_cmd_buffer.c +++ b/src/intel/vulkan/genX_cmd_buffer.c @@ -4867,7 +4867,11 @@ genX(flush_pipeline_select)(struct anv_cmd_buffer *cmd_buffer, */ bits |= ANV_PIPE_CS_STALL_BIT | ANV_PIPE_HDC_PIPELINE_FLUSH_BIT; - if (cmd_buffer->state.current_pipeline == _3D) { + if (cmd_buffer->state.current_pipeline == UINT32_MAX) { + bits |= ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT | + ANV_PIPE_DEPTH_CACHE_FLUSH_BIT | + ANV_PIPE_UNTYPED_DATAPORT_CACHE_FLUSH_BIT; + } else if (cmd_buffer->state.current_pipeline == _3D) { bits |= ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT | ANV_PIPE_DEPTH_CACHE_FLUSH_BIT; } else {