mirror of
https://gitlab.freedesktop.org/mesa/mesa.git
synced 2026-01-06 13:10:10 +01:00
ilo: hook up pipe_screen param and fence functions
This commit is contained in:
Chia-I Wu
Chia-I Wu
parent
e74d67738d
commit
babb2b5c50
3 changed files with 606 additions and 11 deletions
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@ -32,6 +32,28 @@
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#include "ilo_common.h"
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/**
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* \see brw_context.h
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*/
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#define ILO_MAX_DRAW_BUFFERS 8
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#define ILO_MAX_CONST_BUFFERS 1
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#define ILO_MAX_SAMPLER_VIEWS 16
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#define ILO_MAX_SAMPLERS 16
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#define ILO_MAX_SO_BINDINGS 64
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#define ILO_MAX_SO_BUFFERS 4
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#define ILO_MAX_VS_SURFACES (ILO_MAX_CONST_BUFFERS + ILO_MAX_SAMPLER_VIEWS)
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#define ILO_VS_CONST_SURFACE(i) (i)
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#define ILO_VS_TEXTURE_SURFACE(i) (ILO_MAX_CONST_BUFFERS + i)
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#define ILO_MAX_GS_SURFACES (ILO_MAX_SO_BINDINGS)
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#define ILO_GS_SO_SURFACE(i) (i)
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#define ILO_MAX_WM_SURFACES (ILO_MAX_DRAW_BUFFERS + ILO_MAX_CONST_BUFFERS + ILO_MAX_SAMPLER_VIEWS)
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#define ILO_WM_DRAW_SURFACE(i) (i)
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#define ILO_WM_CONST_SURFACE(i) (ILO_MAX_DRAW_BUFFERS + i)
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#define ILO_WM_TEXTURE_SURFACE(i) (ILO_MAX_DRAW_BUFFERS + ILO_MAX_CONST_BUFFERS + i)
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struct intel_winsys;
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struct ilo_screen;
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@ -26,7 +26,10 @@
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*/
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#include "util/u_format_s3tc.h"
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#include "vl/vl_decoder.h"
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#include "vl/vl_video_buffer.h"
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#include "intel_chipset.h"
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#include "intel_reg.h" /* for TIMESTAMP */
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#include "intel_winsys.h"
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#include "ilo_context.h"
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@ -48,6 +51,563 @@ static const struct debug_named_value ilo_debug_flags[] = {
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DEBUG_NAMED_VALUE_END
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};
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static float
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ilo_get_paramf(struct pipe_screen *screen, enum pipe_capf param)
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{
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switch (param) {
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case PIPE_CAPF_MAX_LINE_WIDTH:
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/* in U3.7, defined in 3DSTATE_SF */
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return 7.0f;
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case PIPE_CAPF_MAX_LINE_WIDTH_AA:
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/* line width minus one, which is reserved for AA region */
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return 6.0f;
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case PIPE_CAPF_MAX_POINT_WIDTH:
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/* in U8.3, defined in 3DSTATE_SF */
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return 255.0f;
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case PIPE_CAPF_MAX_POINT_WIDTH_AA:
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/* same as point width, as we ignore rasterizer->point_smooth */
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return 255.0f;
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case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
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/* [2.0, 16.0], defined in SAMPLER_STATE */
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return 16.0f;
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case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
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/* [-16.0, 16.0), defined in SAMPLER_STATE */
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return 15.0f;
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case PIPE_CAPF_GUARD_BAND_LEFT:
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case PIPE_CAPF_GUARD_BAND_TOP:
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case PIPE_CAPF_GUARD_BAND_RIGHT:
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case PIPE_CAPF_GUARD_BAND_BOTTOM:
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/* what are these for? */
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return 0.0f;
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default:
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return 0.0f;
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}
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}
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static int
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ilo_get_shader_param(struct pipe_screen *screen, unsigned shader,
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enum pipe_shader_cap param)
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{
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switch (shader) {
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case PIPE_SHADER_FRAGMENT:
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case PIPE_SHADER_VERTEX:
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case PIPE_SHADER_GEOMETRY:
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break;
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default:
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return 0;
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}
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switch (param) {
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/* the limits are copied from the classic driver */
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case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
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return (shader == PIPE_SHADER_FRAGMENT) ? 1024 : 16384;
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case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
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return (shader == PIPE_SHADER_FRAGMENT) ? 1024 : 0;
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case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
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return (shader == PIPE_SHADER_FRAGMENT) ? 1024 : 0;
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case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
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return (shader == PIPE_SHADER_FRAGMENT) ? 1024 : 0;
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case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
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return UINT_MAX;
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case PIPE_SHADER_CAP_MAX_INPUTS:
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/* this is limited by how many attributes SF can remap */
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return 16;
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case PIPE_SHADER_CAP_MAX_CONSTS:
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return 1024;
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case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
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return ILO_MAX_CONST_BUFFERS;
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case PIPE_SHADER_CAP_MAX_TEMPS:
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return 256;
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case PIPE_SHADER_CAP_MAX_ADDRS:
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return (shader == PIPE_SHADER_FRAGMENT) ? 0 : 1;
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case PIPE_SHADER_CAP_MAX_PREDS:
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return 0;
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case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
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return 1;
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case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
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return 0;
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case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
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return 0;
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case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
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return (shader == PIPE_SHADER_FRAGMENT) ? 0 : 1;
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case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
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return (shader == PIPE_SHADER_FRAGMENT) ? 0 : 1;
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case PIPE_SHADER_CAP_SUBROUTINES:
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return 0;
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case PIPE_SHADER_CAP_INTEGERS:
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return 1;
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case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
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return ILO_MAX_SAMPLERS;
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case PIPE_SHADER_CAP_PREFERRED_IR:
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return PIPE_SHADER_IR_TGSI;
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case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
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return 1;
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default:
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return 0;
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}
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}
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static int
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ilo_get_video_param(struct pipe_screen *screen,
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enum pipe_video_profile profile,
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enum pipe_video_cap param)
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{
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switch (param) {
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case PIPE_VIDEO_CAP_SUPPORTED:
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return vl_profile_supported(screen, profile);
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case PIPE_VIDEO_CAP_NPOT_TEXTURES:
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return 1;
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case PIPE_VIDEO_CAP_MAX_WIDTH:
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case PIPE_VIDEO_CAP_MAX_HEIGHT:
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return vl_video_buffer_max_size(screen);
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case PIPE_VIDEO_CAP_PREFERED_FORMAT:
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return PIPE_FORMAT_NV12;
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case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
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return 1;
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case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
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return 1;
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case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED:
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return 0;
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default:
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return 0;
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}
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}
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static int
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ilo_get_compute_param(struct pipe_screen *screen,
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enum pipe_compute_cap param,
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void *ret)
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{
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union {
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const char *ir_target;
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uint64_t grid_dimension;
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uint64_t max_grid_size[3];
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uint64_t max_block_size[3];
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uint64_t max_threads_per_block;
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uint64_t max_global_size;
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uint64_t max_local_size;
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uint64_t max_private_size;
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uint64_t max_input_size;
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uint64_t max_mem_alloc_size;
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} val;
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const void *ptr;
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int size;
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/* XXX some randomly chosen values */
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switch (param) {
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case PIPE_COMPUTE_CAP_IR_TARGET:
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val.ir_target = "ilog";
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ptr = val.ir_target;
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size = strlen(val.ir_target) + 1;
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break;
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case PIPE_COMPUTE_CAP_GRID_DIMENSION:
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val.grid_dimension = Elements(val.max_grid_size);
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ptr = &val.grid_dimension;
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size = sizeof(val.grid_dimension);
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break;
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case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
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val.max_grid_size[0] = 65535;
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val.max_grid_size[1] = 65535;
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val.max_grid_size[2] = 1;
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ptr = &val.max_grid_size;
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size = sizeof(val.max_grid_size);
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break;
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case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
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val.max_block_size[0] = 512;
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val.max_block_size[1] = 512;
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val.max_block_size[2] = 512;
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ptr = &val.max_block_size;
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size = sizeof(val.max_block_size);
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break;
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case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
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val.max_threads_per_block = 512;
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ptr = &val.max_threads_per_block;
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size = sizeof(val.max_threads_per_block);
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break;
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case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE:
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val.max_global_size = 4;
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ptr = &val.max_global_size;
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size = sizeof(val.max_global_size);
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break;
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case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE:
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val.max_local_size = 64 * 1024;
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ptr = &val.max_local_size;
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size = sizeof(val.max_local_size);
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break;
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case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE:
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val.max_private_size = 32768;
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ptr = &val.max_private_size;
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size = sizeof(val.max_private_size);
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break;
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case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE:
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val.max_input_size = 256;
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ptr = &val.max_input_size;
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size = sizeof(val.max_input_size);
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break;
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case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
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val.max_mem_alloc_size = 128 * 1024 * 1024;
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ptr = &val.max_mem_alloc_size;
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size = sizeof(val.max_mem_alloc_size);
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break;
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default:
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ptr = NULL;
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size = 0;
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break;
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}
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if (ret)
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memcpy(ret, ptr, size);
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return size;
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}
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static int
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ilo_get_param(struct pipe_screen *screen, enum pipe_cap param)
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{
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struct ilo_screen *is = ilo_screen(screen);
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switch (param) {
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case PIPE_CAP_NPOT_TEXTURES:
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case PIPE_CAP_TWO_SIDED_STENCIL:
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return true;
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case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
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return 0; /* TODO */
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case PIPE_CAP_ANISOTROPIC_FILTER:
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case PIPE_CAP_POINT_SPRITE:
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return true;
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case PIPE_CAP_MAX_RENDER_TARGETS:
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return ILO_MAX_DRAW_BUFFERS;
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case PIPE_CAP_OCCLUSION_QUERY:
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case PIPE_CAP_QUERY_TIME_ELAPSED:
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case PIPE_CAP_TEXTURE_SHADOW_MAP:
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case PIPE_CAP_TEXTURE_SWIZZLE: /* must be supported for shadow map */
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return true;
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case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
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/*
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* As defined in SURFACE_STATE, we have
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*
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* Max WxHxD for 2D and CUBE Max WxHxD for 3D
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* GEN6 8192x8192x512 2048x2048x2048
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* GEN7 16384x16384x2048 2048x2048x2048
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*
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* However, when the texutre size is large, things become unstable. We
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* require the maximum texture size to be 2^30 bytes in
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* screen->can_create_resource(). Since the maximum pixel size is 2^4
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* bytes (PIPE_FORMAT_R32G32B32A32_FLOAT), textures should not have more
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* than 2^26 pixels.
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*
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* For 3D textures, we have to set the maximum number of levels to 9,
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* which has at most 2^24 pixels. For 2D textures, we set it to 14,
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* which has at most 2^26 pixels.
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*/
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return 14;
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case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
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return 9;
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case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
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return 14;
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case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
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return false;
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case PIPE_CAP_BLEND_EQUATION_SEPARATE:
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case PIPE_CAP_SM3:
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return true;
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case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
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if (is->gen >= ILO_GEN(7))
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return 0; /* TODO */
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return ILO_MAX_SO_BUFFERS;
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case PIPE_CAP_PRIMITIVE_RESTART:
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return false; /* TODO */
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case PIPE_CAP_MAX_COMBINED_SAMPLERS:
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return ILO_MAX_SAMPLERS * 2;
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case PIPE_CAP_INDEP_BLEND_ENABLE:
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case PIPE_CAP_INDEP_BLEND_FUNC:
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return true;
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case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
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return (is->gen >= ILO_GEN(7)) ? 2048 : 512;
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case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
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case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
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case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
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case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
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case PIPE_CAP_DEPTH_CLIP_DISABLE:
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return true;
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case PIPE_CAP_SHADER_STENCIL_EXPORT:
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return false;
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case PIPE_CAP_TGSI_INSTANCEID:
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case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
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return false; /* TODO */
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case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
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return false;
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case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
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return true;
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case PIPE_CAP_SEAMLESS_CUBE_MAP:
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case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
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case PIPE_CAP_SCALED_RESOLVE:
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return true;
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case PIPE_CAP_MIN_TEXEL_OFFSET:
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return -8;
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case PIPE_CAP_MAX_TEXEL_OFFSET:
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return 7;
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case PIPE_CAP_CONDITIONAL_RENDER:
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case PIPE_CAP_TEXTURE_BARRIER:
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return true;
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case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
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return ILO_MAX_SO_BINDINGS / ILO_MAX_SO_BUFFERS;
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case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
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return ILO_MAX_SO_BINDINGS;
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case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
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return false; /* TODO */
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case PIPE_CAP_TGSI_CAN_COMPACT_VARYINGS:
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case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
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return false;
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case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
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return true;
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case PIPE_CAP_VERTEX_COLOR_CLAMPED:
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return false;
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case PIPE_CAP_GLSL_FEATURE_LEVEL:
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return 130;
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case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
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case PIPE_CAP_USER_VERTEX_BUFFERS:
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return false;
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case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
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case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
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case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
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return false;
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case PIPE_CAP_COMPUTE:
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return false; /* TODO */
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case PIPE_CAP_USER_INDEX_BUFFERS:
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return false;
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case PIPE_CAP_USER_CONSTANT_BUFFERS:
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return false; /* TODO push constants */
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case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
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return 16;
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case PIPE_CAP_START_INSTANCE:
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case PIPE_CAP_QUERY_TIMESTAMP:
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return true;
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case PIPE_CAP_TEXTURE_MULTISAMPLE:
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return false; /* TODO */
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case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
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return 0; /* TODO */
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case PIPE_CAP_CUBE_MAP_ARRAY:
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case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
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return false; /* TODO */
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case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
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return 0; /* TODO */
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case PIPE_CAP_TGSI_TEXCOORD:
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return false;
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case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
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return true;
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case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
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return false; /* TODO */
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case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
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return 0;
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default:
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return 0;
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}
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}
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static const char *
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ilo_get_vendor(struct pipe_screen *screen)
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{
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return "LunarG, Inc.";
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}
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static const char *
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ilo_get_name(struct pipe_screen *screen)
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{
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struct ilo_screen *is = ilo_screen(screen);
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const char *chipset;
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/* stolen from classic i965 */
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switch (is->devid) {
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case PCI_CHIP_SANDYBRIDGE_GT1:
|
||||
case PCI_CHIP_SANDYBRIDGE_GT2:
|
||||
case PCI_CHIP_SANDYBRIDGE_GT2_PLUS:
|
||||
chipset = "Intel(R) Sandybridge Desktop";
|
||||
break;
|
||||
case PCI_CHIP_SANDYBRIDGE_M_GT1:
|
||||
case PCI_CHIP_SANDYBRIDGE_M_GT2:
|
||||
case PCI_CHIP_SANDYBRIDGE_M_GT2_PLUS:
|
||||
chipset = "Intel(R) Sandybridge Mobile";
|
||||
break;
|
||||
case PCI_CHIP_SANDYBRIDGE_S:
|
||||
chipset = "Intel(R) Sandybridge Server";
|
||||
break;
|
||||
case PCI_CHIP_IVYBRIDGE_GT1:
|
||||
case PCI_CHIP_IVYBRIDGE_GT2:
|
||||
chipset = "Intel(R) Ivybridge Desktop";
|
||||
break;
|
||||
case PCI_CHIP_IVYBRIDGE_M_GT1:
|
||||
case PCI_CHIP_IVYBRIDGE_M_GT2:
|
||||
chipset = "Intel(R) Ivybridge Mobile";
|
||||
break;
|
||||
case PCI_CHIP_IVYBRIDGE_S_GT1:
|
||||
case PCI_CHIP_IVYBRIDGE_S_GT2:
|
||||
chipset = "Intel(R) Ivybridge Server";
|
||||
break;
|
||||
case PCI_CHIP_BAYTRAIL_M_1:
|
||||
case PCI_CHIP_BAYTRAIL_M_2:
|
||||
case PCI_CHIP_BAYTRAIL_M_3:
|
||||
case PCI_CHIP_BAYTRAIL_M_4:
|
||||
case PCI_CHIP_BAYTRAIL_D:
|
||||
chipset = "Intel(R) Bay Trail";
|
||||
break;
|
||||
case PCI_CHIP_HASWELL_GT1:
|
||||
case PCI_CHIP_HASWELL_GT2:
|
||||
case PCI_CHIP_HASWELL_GT2_PLUS:
|
||||
case PCI_CHIP_HASWELL_SDV_GT1:
|
||||
case PCI_CHIP_HASWELL_SDV_GT2:
|
||||
case PCI_CHIP_HASWELL_SDV_GT2_PLUS:
|
||||
case PCI_CHIP_HASWELL_ULT_GT1:
|
||||
case PCI_CHIP_HASWELL_ULT_GT2:
|
||||
case PCI_CHIP_HASWELL_ULT_GT2_PLUS:
|
||||
case PCI_CHIP_HASWELL_CRW_GT1:
|
||||
case PCI_CHIP_HASWELL_CRW_GT2:
|
||||
case PCI_CHIP_HASWELL_CRW_GT2_PLUS:
|
||||
chipset = "Intel(R) Haswell Desktop";
|
||||
break;
|
||||
case PCI_CHIP_HASWELL_M_GT1:
|
||||
case PCI_CHIP_HASWELL_M_GT2:
|
||||
case PCI_CHIP_HASWELL_M_GT2_PLUS:
|
||||
case PCI_CHIP_HASWELL_SDV_M_GT1:
|
||||
case PCI_CHIP_HASWELL_SDV_M_GT2:
|
||||
case PCI_CHIP_HASWELL_SDV_M_GT2_PLUS:
|
||||
case PCI_CHIP_HASWELL_ULT_M_GT1:
|
||||
case PCI_CHIP_HASWELL_ULT_M_GT2:
|
||||
case PCI_CHIP_HASWELL_ULT_M_GT2_PLUS:
|
||||
case PCI_CHIP_HASWELL_CRW_M_GT1:
|
||||
case PCI_CHIP_HASWELL_CRW_M_GT2:
|
||||
case PCI_CHIP_HASWELL_CRW_M_GT2_PLUS:
|
||||
chipset = "Intel(R) Haswell Mobile";
|
||||
break;
|
||||
case PCI_CHIP_HASWELL_S_GT1:
|
||||
case PCI_CHIP_HASWELL_S_GT2:
|
||||
case PCI_CHIP_HASWELL_S_GT2_PLUS:
|
||||
case PCI_CHIP_HASWELL_SDV_S_GT1:
|
||||
case PCI_CHIP_HASWELL_SDV_S_GT2:
|
||||
case PCI_CHIP_HASWELL_SDV_S_GT2_PLUS:
|
||||
case PCI_CHIP_HASWELL_ULT_S_GT1:
|
||||
case PCI_CHIP_HASWELL_ULT_S_GT2:
|
||||
case PCI_CHIP_HASWELL_ULT_S_GT2_PLUS:
|
||||
case PCI_CHIP_HASWELL_CRW_S_GT1:
|
||||
case PCI_CHIP_HASWELL_CRW_S_GT2:
|
||||
case PCI_CHIP_HASWELL_CRW_S_GT2_PLUS:
|
||||
chipset = "Intel(R) Haswell Server";
|
||||
break;
|
||||
default:
|
||||
chipset = "Unknown Intel Chipset";
|
||||
break;
|
||||
}
|
||||
|
||||
return chipset;
|
||||
}
|
||||
|
||||
static uint64_t
|
||||
ilo_get_timestamp(struct pipe_screen *screen)
|
||||
{
|
||||
struct ilo_screen *is = ilo_screen(screen);
|
||||
union {
|
||||
uint64_t val;
|
||||
uint32_t dw[2];
|
||||
} timestamp;
|
||||
|
||||
is->winsys->read_reg(is->winsys, TIMESTAMP, ×tamp.val);
|
||||
|
||||
/*
|
||||
* From the Ivy Bridge PRM, volume 1 part 3, page 107:
|
||||
*
|
||||
* "Note: This timestamp register reflects the value of the PCU TSC.
|
||||
* The PCU TSC counts 10ns increments; this timestamp reflects bits
|
||||
* 38:3 of the TSC (i.e. 80ns granularity, rolling over every 1.5
|
||||
* hours)."
|
||||
*
|
||||
* However, it seems dw[0] is garbage and dw[1] contains the lower 32 bits
|
||||
* of the timestamp. We will have to live with a timestamp that rolls over
|
||||
* every ~343 seconds.
|
||||
*
|
||||
* See also brw_get_timestamp().
|
||||
*/
|
||||
return (uint64_t) timestamp.dw[1] * 80;
|
||||
}
|
||||
|
||||
static void
|
||||
ilo_fence_reference(struct pipe_screen *screen,
|
||||
struct pipe_fence_handle **p,
|
||||
struct pipe_fence_handle *f)
|
||||
{
|
||||
struct ilo_fence **ptr = (struct ilo_fence **) p;
|
||||
struct ilo_fence *fence = ilo_fence(f);
|
||||
|
||||
if (!ptr) {
|
||||
/* still need to reference fence */
|
||||
if (fence)
|
||||
pipe_reference(NULL, &fence->reference);
|
||||
return;
|
||||
}
|
||||
|
||||
/* reference fence and dereference the one pointed to by ptr */
|
||||
if (*ptr && pipe_reference(&(*ptr)->reference, &fence->reference)) {
|
||||
struct ilo_fence *old = *ptr;
|
||||
|
||||
if (old->bo)
|
||||
old->bo->unreference(old->bo);
|
||||
FREE(old);
|
||||
}
|
||||
|
||||
*ptr = fence;
|
||||
}
|
||||
|
||||
static boolean
|
||||
ilo_fence_signalled(struct pipe_screen *screen,
|
||||
struct pipe_fence_handle *f)
|
||||
{
|
||||
struct ilo_fence *fence = ilo_fence(f);
|
||||
|
||||
/* mark signalled if the bo is idle */
|
||||
if (fence->bo && !intel_bo_is_busy(fence->bo)) {
|
||||
fence->bo->unreference(fence->bo);
|
||||
fence->bo = NULL;
|
||||
}
|
||||
|
||||
return (fence->bo == NULL);
|
||||
}
|
||||
|
||||
static boolean
|
||||
ilo_fence_finish(struct pipe_screen *screen,
|
||||
struct pipe_fence_handle *f,
|
||||
uint64_t timeout)
|
||||
{
|
||||
struct ilo_fence *fence = ilo_fence(f);
|
||||
const int64_t wait_timeout = (timeout > INT64_MAX) ? -1 : timeout;
|
||||
|
||||
/* already signalled */
|
||||
if (!fence->bo)
|
||||
return true;
|
||||
|
||||
/* wait and see if it returns error */
|
||||
if (fence->bo->wait(fence->bo, wait_timeout))
|
||||
return false;
|
||||
|
||||
/* mark signalled */
|
||||
fence->bo->unreference(fence->bo);
|
||||
fence->bo = NULL;
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
static void
|
||||
ilo_screen_destroy(struct pipe_screen *screen)
|
||||
{
|
||||
|
|
@ -93,21 +653,21 @@ ilo_screen_create(struct intel_winsys *ws)
|
|||
util_format_s3tc_init();
|
||||
|
||||
is->base.destroy = ilo_screen_destroy;
|
||||
is->base.get_name = NULL;
|
||||
is->base.get_vendor = NULL;
|
||||
is->base.get_param = NULL;
|
||||
is->base.get_paramf = NULL;
|
||||
is->base.get_shader_param = NULL;
|
||||
is->base.get_video_param = NULL;
|
||||
is->base.get_compute_param = NULL;
|
||||
is->base.get_name = ilo_get_name;
|
||||
is->base.get_vendor = ilo_get_vendor;
|
||||
is->base.get_param = ilo_get_param;
|
||||
is->base.get_paramf = ilo_get_paramf;
|
||||
is->base.get_shader_param = ilo_get_shader_param;
|
||||
is->base.get_video_param = ilo_get_video_param;
|
||||
is->base.get_compute_param = ilo_get_compute_param;
|
||||
|
||||
is->base.get_timestamp = NULL;
|
||||
is->base.get_timestamp = ilo_get_timestamp;
|
||||
|
||||
is->base.flush_frontbuffer = NULL;
|
||||
|
||||
is->base.fence_reference = NULL;
|
||||
is->base.fence_signalled = NULL;
|
||||
is->base.fence_finish = NULL;
|
||||
is->base.fence_reference = ilo_fence_reference;
|
||||
is->base.fence_signalled = ilo_fence_signalled;
|
||||
is->base.fence_finish = ilo_fence_finish;
|
||||
|
||||
is->base.get_driver_query_info = NULL;
|
||||
|
||||
|
|
|
|||
|
|
@ -29,10 +29,17 @@
|
|||
#define ILO_SCREEN_H
|
||||
|
||||
#include "pipe/p_screen.h"
|
||||
#include "pipe/p_state.h"
|
||||
|
||||
#include "ilo_common.h"
|
||||
|
||||
struct intel_winsys;
|
||||
struct intel_bo;
|
||||
|
||||
struct ilo_fence {
|
||||
struct pipe_reference reference;
|
||||
struct intel_bo *bo;
|
||||
};
|
||||
|
||||
struct ilo_screen {
|
||||
struct pipe_screen base;
|
||||
|
|
@ -50,4 +57,10 @@ ilo_screen(struct pipe_screen *screen)
|
|||
return (struct ilo_screen *) screen;
|
||||
}
|
||||
|
||||
static inline struct ilo_fence *
|
||||
ilo_fence(struct pipe_fence_handle *fence)
|
||||
{
|
||||
return (struct ilo_fence *) fence;
|
||||
}
|
||||
|
||||
#endif /* ILO_SCREEN_H */
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue