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intel/fs: Handle payload node interference in destinations

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Starting with d0d039a4d3, we emit writes to the push constant chunk
of the payload to stomp out-of-bounds data to zero for Vulkan.  Then, in
369eab9420, we started emitting shader preamble code for emulated
push constants on Gen12.5 parts.  In either of these cases, we can run
into issues if we don't have a proper live range for some of the payload
registers where they get used for something and then smashed by our push
handling code.  We've not seen many issues with this yet because it only
happens when you have dead push constants.

Fixes: d0d039a4d3 "anv: Emit pushed UBO bounds checking code..."
Fixes: 369eab9420 "intel/fs: Emit code for Gen12-HP indirect..."
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9501>
This commit is contained in:
Jason Ekstrand 2021-03-10 13:19:53 -06:00 • committed by Marge Bot
parent 8b7c2f1800
commit b9e9f92f73
1 changed files with 10 additions and 0 deletions
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10
src/intel/compiler/brw_fs_reg_allocate.cpp
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@ -384,6 +384,16 @@ void fs_visitor::calculate_payload_ranges(int payload_node_count,
}
}
if (inst->dst.file == FIXED_GRF) {
int node_nr = inst->dst.nr;
if (node_nr < payload_node_count) {
for (unsigned j = 0; j < regs_written(inst); j++) {
payload_last_use_ip[node_nr + j] = use_ip;
assert(node_nr + j < unsigned(payload_node_count));
}
}
}
/* Special case instructions which have extra implied registers used. */
switch (inst->opcode) {
case CS_OPCODE_CS_TERMINATE: