radv,radeonsi: Disable compression on interop depth images

If we want to use HTILE correctly we need to communicate extra stuff
like clear colors. (Unlike DCC there is no HTILE FCE)

CC: mesa-stable
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
(cherry picked from commit d78df70c2a)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6877>

.pick_status.json

@@ -4243,7 +4243,7 @@
         "description": "radv,radeonsi: Disable compression on interop depth images",
         "nominated": true,
         "nomination_type": 0,
-        "resolution": 0,
+        "resolution": 3,
         "master_sha": null,
         "because_sha": null
     },

src/amd/vulkan/radv_image.c

@@ -261,6 +261,7 @@ static inline bool
 radv_use_htile_for_image(const struct radv_image *image)
 {
 	return image->info.levels == 1 &&
+	       !image->shareable &&
 	       image->info.width * image->info.height >= 8 * 8;
 }
 

src/gallium/drivers/radeonsi/si_texture.c

@@ -237,7 +237,8 @@ static int si_init_surface(struct si_screen *sscreen, struct radeon_surf *surfac
    if (!is_flushed_depth && is_depth) {
       flags |= RADEON_SURF_ZBUFFER;
 
-      if (sscreen->debug_flags & DBG(NO_HYPERZ)) {
+      if ((sscreen->debug_flags & DBG(NO_HYPERZ)) ||
+          (ptex->bind & PIPE_BIND_SHARED) || is_imported) {
          flags |= RADEON_SURF_NO_HTILE;
       } else if (tc_compatible_htile &&
                  (sscreen->info.chip_class >= GFX9 || array_mode == RADEON_SURF_MODE_2D)) {