mirror of
https://gitlab.freedesktop.org/mesa/mesa.git
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amd/drm-shim: Add raphael&mendocino, polaris12 and gfx1100.
Decided to follow the chip names pretty much.This set happens to be what is in my workstation currently. Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22975>
This commit is contained in:
Bas Nieuwenhuizen
Marge Bot
parent
d16cd4c758
commit
b96aa6b9e2
1 changed files with 442 additions and 0 deletions
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@ -636,6 +636,448 @@ static const struct amdgpu_device amdgpu_devices[] = {
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.max_allocation = 6383253504,
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},
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},
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},
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{
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.name = "raphael_mendocino",
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.radeon_family = CHIP_RAPHAEL_MENDOCINO,
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.hw_ip_gfx = {
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.hw_ip_version_major = 10,
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.hw_ip_version_minor = 0,
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.capabilities_flags = 0llu,
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.ib_start_alignment = 32,
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.ib_size_alignment = 32,
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.available_rings = 0x1,
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.ip_discovery_version = 0xa0306,
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},
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.hw_ip_compute = {
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.hw_ip_version_major = 10,
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.hw_ip_version_minor = 0,
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.capabilities_flags = 0llu,
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.ib_start_alignment = 32,
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.ib_size_alignment = 32,
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.available_rings = 0xf,
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.ip_discovery_version = 0xa0306,
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},
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.fw_gfx_me = {
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.ver = 13,
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.feature = 38,
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},
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.fw_gfx_pfp = {
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.ver = 13,
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.feature = 38,
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},
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.fw_gfx_mec = {
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.ver = 18,
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.feature = 38,
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},
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.mmr_regs = {
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0x263e, 0xffffffff, 0x00000042,
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},
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.mmr_reg_count = 1,
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.dev = {
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.device_id = 0x164e,
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.chip_rev = 0x01,
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.external_rev = 0x02,
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.pci_rev = 0xc1,
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.family = AMDGPU_FAMILY_GC_10_3_6,
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.num_shader_engines = 1,
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.num_shader_arrays_per_engine = 1,
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.gpu_counter_freq = 100000,
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.max_engine_clock = 200000llu,
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.max_memory_clock = 2400000llu,
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.cu_active_number = 2,
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.cu_ao_mask = 0x3,
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.cu_bitmap = {
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{ 0x3, 0x0, 0x0, 0x0, },
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{ 0x0, 0x0, 0x0, 0x0, },
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{ 0x0, 0x0, 0x0, 0x0, },
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{ 0x0, 0x0, 0x0, 0x0, },
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},
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.enabled_rb_pipes_mask = 0x1,
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.num_rb_pipes = 1,
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.num_hw_gfx_contexts = 8,
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.pcie_gen = 4,
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.ids_flags = 0x1llu,
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.virtual_address_offset = 0x200000llu,
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.virtual_address_max = 0x800000000000llu,
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.virtual_address_alignment = 4096,
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.pte_fragment_size = 2097152,
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.gart_page_size = 4096,
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.ce_ram_size = 65536,
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.vram_type = 10,
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.vram_bit_width = 128,
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.vce_harvest_config = 0,
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.gc_double_offchip_lds_buf = 1,
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.prim_buf_gpu_addr = 0llu,
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.pos_buf_gpu_addr = 0llu,
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.cntl_sb_buf_gpu_addr = 0llu,
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.param_buf_gpu_addr = 0llu,
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.prim_buf_size = 0,
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.pos_buf_size = 0,
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.cntl_sb_buf_size = 0,
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.param_buf_size = 0,
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.wave_front_size = 32,
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.num_shader_visible_vgprs = 1024,
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.num_cu_per_sh = 2,
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.num_tcc_blocks = 2,
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.gs_vgt_table_depth = 32,
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.gs_prim_buffer_depth = 1792,
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.max_gs_waves_per_vgt = 32,
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.pcie_num_lanes = 16,
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.cu_ao_bitmap = {
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{ 0x3, 0x0, 0x0, 0x0, },
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{ 0x0, 0x0, 0x0, 0x0, },
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{ 0x0, 0x0, 0x0, 0x0, },
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{ 0x0, 0x0, 0x0, 0x0, },
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},
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.high_va_offset = 0xffff800000000000llu,
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.high_va_max = 0xffffffffffe00000llu,
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.pa_sc_tile_steering_override = 0,
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.tcc_disabled_mask = 0llu,
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.min_engine_clock = 200000llu,
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.min_memory_clock = 2400000llu,
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.tcp_cache_size = 0,
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.num_sqc_per_wgp = 0,
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.sqc_data_cache_size = 0,
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.sqc_inst_cache_size = 0,
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.gl1c_cache_size = 0,
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.gl2c_cache_size = 0,
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.mall_size = 0llu,
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.enabled_rb_pipes_mask_hi = 0,
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},
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.mem = {
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.vram = {
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.total_heap_size = 536870912,
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.usable_heap_size = 512081920,
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.heap_usage = 30093312,
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.max_allocation = 384061440,
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},
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.cpu_accessible_vram = {
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.total_heap_size = 536870912,
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.usable_heap_size = 512081920,
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.heap_usage = 30093312,
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.max_allocation = 384061440,
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},
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.gtt = {
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.total_heap_size = 33254252544,
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.usable_heap_size = 33241997312,
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.heap_usage = 14360576,
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.max_allocation = 24931497984,
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},
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},
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},
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{
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.name = "polaris12",
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.radeon_family = CHIP_POLARIS12,
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.hw_ip_gfx = {
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.hw_ip_version_major = 8,
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.hw_ip_version_minor = 0,
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.capabilities_flags = 0llu,
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.ib_start_alignment = 32,
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.ib_size_alignment = 32,
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.available_rings = 0x1,
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.ip_discovery_version = 0x0000,
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},
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.hw_ip_compute = {
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.hw_ip_version_major = 8,
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.hw_ip_version_minor = 0,
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.capabilities_flags = 0llu,
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.ib_start_alignment = 32,
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.ib_size_alignment = 32,
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.available_rings = 0xf,
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.ip_discovery_version = 0x0000,
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},
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.fw_gfx_me = {
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.ver = 167,
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.feature = 49,
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},
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.fw_gfx_pfp = {
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.ver = 254,
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.feature = 49,
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},
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.fw_gfx_mec = {
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.ver = 730,
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.feature = 49,
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},
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.mmr_regs = {
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0x263e, 0xffffffff, 0x22011002,
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0x263d, 0x0000ff00, 0x00000001,
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0xa0d4, 0x0000ff00, 0x16000012,
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0xa0d5, 0x0000ff00, 0x00000000,
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0x263d, 0x0000ff01, 0x00000001,
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0xa0d4, 0x0000ff01, 0x16000012,
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0xa0d5, 0x0000ff01, 0x00000000,
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0x09d8, 0xffffffff, 0x000060a2,
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0x2644, 0xffffffff, 0x00800150,
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0x2645, 0xffffffff, 0x00800950,
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0x2646, 0xffffffff, 0x00801150,
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0x2647, 0xffffffff, 0x00801950,
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0x2648, 0xffffffff, 0x00802950,
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0x2649, 0xffffffff, 0x00802948,
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0x264a, 0xffffffff, 0x00802954,
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0x264b, 0xffffffff, 0x00802954,
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0x264c, 0xffffffff, 0x00000144,
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0x264d, 0xffffffff, 0x02000148,
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0x264e, 0xffffffff, 0x02000150,
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0x264f, 0xffffffff, 0x06000154,
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0x2650, 0xffffffff, 0x06000154,
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0x2651, 0xffffffff, 0x02400148,
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0x2652, 0xffffffff, 0x02400150,
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0x2653, 0xffffffff, 0x02400170,
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0x2654, 0xffffffff, 0x06400154,
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0x2655, 0xffffffff, 0x06400154,
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0x2656, 0xffffffff, 0x0040014c,
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0x2657, 0xffffffff, 0x0100014c,
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0x2658, 0xffffffff, 0x0100015c,
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0x2659, 0xffffffff, 0x01000174,
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0x265a, 0xffffffff, 0x01000164,
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0x265b, 0xffffffff, 0x01000164,
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0x265c, 0xffffffff, 0x0040015c,
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0x265d, 0xffffffff, 0x01000160,
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0x265e, 0xffffffff, 0x01000178,
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0x265f, 0xffffffff, 0x02c00148,
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0x2660, 0xffffffff, 0x02c00150,
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0x2661, 0xffffffff, 0x06c00154,
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0x2662, 0xffffffff, 0x06c00154,
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0x2663, 0xffffffff, 0x00000000,
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0x2664, 0xffffffff, 0x000000e8,
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0x2665, 0xffffffff, 0x000000e8,
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0x2666, 0xffffffff, 0x000000e8,
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0x2667, 0xffffffff, 0x000000e4,
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0x2668, 0xffffffff, 0x000000d0,
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0x2669, 0xffffffff, 0x000000d0,
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0x266a, 0xffffffff, 0x000000d0,
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0x266b, 0xffffffff, 0x00000000,
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0x266c, 0xffffffff, 0x000000ed,
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0x266d, 0xffffffff, 0x000000e9,
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0x266e, 0xffffffff, 0x000000e8,
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0x266f, 0xffffffff, 0x000000e4,
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0x2670, 0xffffffff, 0x000000d0,
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0x2671, 0xffffffff, 0x00000090,
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0x2672, 0xffffffff, 0x00000040,
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0x2673, 0xffffffff, 0x00000000,
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},
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.mmr_reg_count = 56,
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.dev = {
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.device_id = 0x699f,
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.chip_rev = 0x00,
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.external_rev = 0x64,
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.pci_rev = 0xc7,
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.family = AMDGPU_FAMILY_VI,
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.num_shader_engines = 2,
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.num_shader_arrays_per_engine = 1,
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.gpu_counter_freq = 25000,
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.max_engine_clock = 1183000llu,
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.max_memory_clock = 1750000llu,
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.cu_active_number = 8,
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.cu_ao_mask = 0x1e001e,
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.cu_bitmap = {
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{ 0x1e, 0x0, 0x0, 0x0, },
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{ 0x1e, 0x0, 0x0, 0x0, },
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{ 0x0, 0x0, 0x0, 0x0, },
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{ 0x0, 0x0, 0x0, 0x0, },
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},
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.enabled_rb_pipes_mask = 0xf,
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.num_rb_pipes = 4,
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.num_hw_gfx_contexts = 8,
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.pcie_gen = 3,
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.ids_flags = 0x0llu,
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.virtual_address_offset = 0x200000llu,
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.virtual_address_max = 0x3fffe00000llu,
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.virtual_address_alignment = 4096,
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.pte_fragment_size = 2097152,
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.gart_page_size = 4096,
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.ce_ram_size = 32768,
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.vram_type = 5,
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.vram_bit_width = 128,
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.vce_harvest_config = 2,
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.gc_double_offchip_lds_buf = 1,
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.prim_buf_gpu_addr = 0llu,
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.pos_buf_gpu_addr = 0llu,
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.cntl_sb_buf_gpu_addr = 0llu,
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.param_buf_gpu_addr = 0llu,
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.prim_buf_size = 0,
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.pos_buf_size = 0,
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.cntl_sb_buf_size = 0,
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.param_buf_size = 0,
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.wave_front_size = 64,
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.num_shader_visible_vgprs = 256,
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.num_cu_per_sh = 5,
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.num_tcc_blocks = 4,
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.gs_vgt_table_depth = 0,
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.gs_prim_buffer_depth = 0,
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.max_gs_waves_per_vgt = 32,
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.pcie_num_lanes = 1,
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.cu_ao_bitmap = {
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{ 0x1e, 0x0, 0x0, 0x0, },
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{ 0x1e, 0x0, 0x0, 0x0, },
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{ 0x0, 0x0, 0x0, 0x0, },
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{ 0x0, 0x0, 0x0, 0x0, },
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},
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.high_va_offset = 0x0llu,
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.high_va_max = 0x0llu,
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.pa_sc_tile_steering_override = 0,
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.tcc_disabled_mask = 0llu,
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.min_engine_clock = 214000llu,
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.min_memory_clock = 300000llu,
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.tcp_cache_size = 0,
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.num_sqc_per_wgp = 0,
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.sqc_data_cache_size = 0,
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.sqc_inst_cache_size = 0,
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.gl1c_cache_size = 0,
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.gl2c_cache_size = 0,
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.mall_size = 0llu,
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.enabled_rb_pipes_mask_hi = 0,
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},
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.mem = {
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.vram = {
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.total_heap_size = 4294967296,
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.usable_heap_size = 4281139200,
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.heap_usage = 5963776,
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.max_allocation = 3210854400,
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},
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.cpu_accessible_vram = {
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.total_heap_size = 4294967296,
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.usable_heap_size = 4281139200,
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.heap_usage = 5963776,
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.max_allocation = 3210854400,
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},
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.gtt = {
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.total_heap_size = 33254252544,
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.usable_heap_size = 33249120256,
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.heap_usage = 17903616,
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.max_allocation = 24936840192,
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},
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},
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},
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{
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.name = "gfx1100",
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.radeon_family = CHIP_GFX1100,
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.hw_ip_gfx = {
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.hw_ip_version_major = 11,
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.hw_ip_version_minor = 0,
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.capabilities_flags = 0llu,
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.ib_start_alignment = 32,
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.ib_size_alignment = 32,
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.available_rings = 0x1,
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.ip_discovery_version = 0xb0000,
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},
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.hw_ip_compute = {
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.hw_ip_version_major = 11,
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.hw_ip_version_minor = 0,
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.capabilities_flags = 0llu,
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.ib_start_alignment = 32,
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.ib_size_alignment = 32,
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.available_rings = 0xf,
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.ip_discovery_version = 0xb0000,
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},
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.fw_gfx_me = {
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.ver = 1486,
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.feature = 29,
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},
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.fw_gfx_pfp = {
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.ver = 1525,
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.feature = 29,
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},
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.fw_gfx_mec = {
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.ver = 494,
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.feature = 29,
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},
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.mmr_regs = {
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0x263e, 0xffffffff, 0x00000545,
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},
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.mmr_reg_count = 1,
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.dev = {
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.device_id = 0x744c,
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.chip_rev = 0x00,
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.external_rev = 0x01,
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.pci_rev = 0xc8,
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.family = AMDGPU_FAMILY_GC_11_0_0,
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.num_shader_engines = 6,
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.num_shader_arrays_per_engine = 2,
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.gpu_counter_freq = 100000,
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.max_engine_clock = 2371000llu,
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.max_memory_clock = 1249000llu,
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.cu_active_number = 96,
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.cu_ao_mask = 0x0,
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.cu_bitmap = {
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{ 0xff, 0xff, 0xff, 0xff, },
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{ 0xff, 0xff, 0xff, 0xff, },
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{ 0xff, 0xff, 0x0, 0x0, },
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{ 0xff, 0xff, 0x0, 0x0, },
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},
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.enabled_rb_pipes_mask = 0xffffff,
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.num_rb_pipes = 24,
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.num_hw_gfx_contexts = 8,
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.pcie_gen = 4,
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.ids_flags = 0x0llu,
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.virtual_address_offset = 0x200000llu,
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||||
.virtual_address_max = 0x800000000000llu,
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.virtual_address_alignment = 4096,
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.pte_fragment_size = 2097152,
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.gart_page_size = 4096,
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.ce_ram_size = 0,
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.vram_type = 9,
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.vram_bit_width = 384,
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.vce_harvest_config = 0,
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.gc_double_offchip_lds_buf = 0,
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.prim_buf_gpu_addr = 0llu,
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.pos_buf_gpu_addr = 0llu,
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.cntl_sb_buf_gpu_addr = 0llu,
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.param_buf_gpu_addr = 0llu,
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.prim_buf_size = 0,
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.pos_buf_size = 0,
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.cntl_sb_buf_size = 0,
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.param_buf_size = 0,
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.wave_front_size = 32,
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.num_shader_visible_vgprs = 1536,
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||||
.num_cu_per_sh = 8,
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.num_tcc_blocks = 24,
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.gs_vgt_table_depth = 32,
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.gs_prim_buffer_depth = 1792,
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.max_gs_waves_per_vgt = 32,
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.pcie_num_lanes = 16,
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.cu_ao_bitmap = {
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{ 0x0, 0x0, 0x0, 0x0, },
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{ 0x0, 0x0, 0x0, 0x0, },
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{ 0x0, 0x0, 0x0, 0x0, },
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{ 0x0, 0x0, 0x0, 0x0, },
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},
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.high_va_offset = 0xffff800000000000llu,
|
||||
.high_va_max = 0xffffffffffe00000llu,
|
||||
.pa_sc_tile_steering_override = 0,
|
||||
.tcc_disabled_mask = 0llu,
|
||||
.min_engine_clock = 500000llu,
|
||||
.min_memory_clock = 96000llu,
|
||||
.tcp_cache_size = 32,
|
||||
.num_sqc_per_wgp = 1,
|
||||
.sqc_data_cache_size = 16,
|
||||
.sqc_inst_cache_size = 32,
|
||||
.gl1c_cache_size = 256,
|
||||
.gl2c_cache_size = 6144,
|
||||
.mall_size = 100663296llu,
|
||||
.enabled_rb_pipes_mask_hi = 0,
|
||||
},
|
||||
.mem = {
|
||||
.vram = {
|
||||
.total_heap_size = 25753026560,
|
||||
.usable_heap_size = 25681096704,
|
||||
.heap_usage = 7515435008,
|
||||
.max_allocation = 19260822528,
|
||||
},
|
||||
.cpu_accessible_vram = {
|
||||
.total_heap_size = 25753026560,
|
||||
.usable_heap_size = 25681096704,
|
||||
.heap_usage = 7515435008,
|
||||
.max_allocation = 19260822528,
|
||||
},
|
||||
.gtt = {
|
||||
.total_heap_size = 33254252544,
|
||||
.usable_heap_size = 33240895488,
|
||||
.heap_usage = 142462976,
|
||||
.max_allocation = 24930671616,
|
||||
},
|
||||
},
|
||||
}
|
||||
};
|
||||
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue