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nir: add Intel RT write intrinsic

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This exposes the underlying render target write message directly, which Jay will
use to lower RT writes in NIR. I'm still on the fence about what exactly this
should look like but this is good enough for GLES3.0 (so, multiple render
targets but not necessarily dual source blending).

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40835>
This commit is contained in:
Alyssa Rosenzweig 2025-12-11 12:39:57 -05:00 • committed by Marge Bot
parent 566047222e
commit b840b178af
1 changed files with 8 additions and 0 deletions
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8
src/compiler/nir/nir_intrinsics.py
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@ -383,6 +383,10 @@ index("bool", "explicit_coord")
index("bool", "src_is_reg")
index("bool", "dst_is_reg")
# For an Intel render target store, whether this signals end-of-thread. Must be
# the last instruction.
index("bool", "eot")
# The index of the format string used by a printf. (u_printf_info element of the shader)
index("unsigned", "fmt_idx")
# for NV coop matrix - num of matrix in load 1/2/4
@ -2614,6 +2618,10 @@ system_value("indirect_address_intel", 1)
intrinsic("load_reloc_const_intel", dest_comp=1, bit_sizes=[32],
indices=[PARAM_IDX, BASE], flags=[CAN_ELIMINATE, CAN_REORDER])
# Write a render target
# src[] = { payload, 2x32 descriptor, predicate }
intrinsic("store_render_target_intel", [-1, 2, 1], indices=[EOT], bit_sizes=[32])
# 1 component 32bit surface index that can be used for bindless or BTI heaps
#
# This intrinsic is used to figure out what UBOs accesses could be promoted to