From b840b178aff85a79e47877e0fba751d5620a76fc Mon Sep 17 00:00:00 2001 From: Alyssa Rosenzweig Date: Thu, 11 Dec 2025 12:39:57 -0500 Subject: [PATCH] nir: add Intel RT write intrinsic This exposes the underlying render target write message directly, which Jay will use to lower RT writes in NIR. I'm still on the fence about what exactly this should look like but this is good enough for GLES3.0 (so, multiple render targets but not necessarily dual source blending). Signed-off-by: Alyssa Rosenzweig Reviewed-by: Lionel Landwerlin Reviewed-by: Kenneth Graunke Part-of: --- src/compiler/nir/nir_intrinsics.py | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/src/compiler/nir/nir_intrinsics.py b/src/compiler/nir/nir_intrinsics.py index 37e07cc1fc4..8f2a3ccb16a 100644 --- a/src/compiler/nir/nir_intrinsics.py +++ b/src/compiler/nir/nir_intrinsics.py @@ -383,6 +383,10 @@ index("bool", "explicit_coord") index("bool", "src_is_reg") index("bool", "dst_is_reg") +# For an Intel render target store, whether this signals end-of-thread. Must be +# the last instruction. +index("bool", "eot") + # The index of the format string used by a printf. (u_printf_info element of the shader) index("unsigned", "fmt_idx") # for NV coop matrix - num of matrix in load 1/2/4 @@ -2614,6 +2618,10 @@ system_value("indirect_address_intel", 1) intrinsic("load_reloc_const_intel", dest_comp=1, bit_sizes=[32], indices=[PARAM_IDX, BASE], flags=[CAN_ELIMINATE, CAN_REORDER]) +# Write a render target +# src[] = { payload, 2x32 descriptor, predicate } +intrinsic("store_render_target_intel", [-1, 2, 1], indices=[EOT], bit_sizes=[32]) + # 1 component 32bit surface index that can be used for bindless or BTI heaps # # This intrinsic is used to figure out what UBOs accesses could be promoted to