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iris: Allocate fixed amount of space for blend state.

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According to the simulator a cacheline of the blend state cache
corresponds to 3 cachelines of L3 that are always filled regardless of
the number of render targets in use.  Allocate enough space to avoid
pagefaults under simulation, since a scratch page isn't bound by
default.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28283>
This commit is contained in:
Francisco Jerez 2022-08-24 11:29:46 -07:00 • committed by Marge Bot
parent 8f798cc911
commit b73638ae5e
1 changed files with 1 additions and 2 deletions
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3
src/gallium/drivers/iris/iris_state.c
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@ -6865,7 +6865,6 @@ iris_upload_dirty_render_state(struct iris_context *ice,
struct iris_blend_state *cso_blend = ice->state.cso_blend;
struct pipe_framebuffer_state *cso_fb = &ice->state.framebuffer;
struct iris_depth_stencil_alpha_state *cso_zsa = ice->state.cso_zsa;
const int header_dwords = GENX(BLEND_STATE_length);
bool color_blend_zero = false;
bool alpha_blend_zero = false;
@ -6881,7 +6880,7 @@ iris_upload_dirty_render_state(struct iris_context *ice,
uint32_t *blend_map =
stream_state(batch, ice->state.dynamic_uploader,
&ice->state.last_res.blend,
4 * (header_dwords + rt_dwords), 64, &blend_offset);
96, 64, &blend_offset);
/* Copy of blend entries for merging dynamic changes. */
uint32_t blend_entries[4 * rt_dwords];