intel/brw/xe2+: Fix indirect extended descriptor setup for scratch space.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28283>
This commit is contained in:
Francisco Jerez 2022-08-24 11:27:52 -07:00 committed by Marge Bot
parent 0d92ec44e5
commit 8f798cc911

View file

@ -1550,14 +1550,22 @@ brw_send_indirect_split_message(struct brw_codegen *p,
unsigned imm_part = ex_bso ? 0 : (ex_desc_imm | sfid | eot << 5);
if (ex_desc_scratch) {
/* Or the scratch surface offset together with the immediate part of
* the extended descriptor.
*/
assert(devinfo->verx10 >= 125);
brw_AND(p, addr,
retype(brw_vec1_grf(0, 5), BRW_TYPE_UD),
brw_imm_ud(INTEL_MASK(31, 10)));
brw_OR(p, addr, addr, brw_imm_ud(imm_part));
if (devinfo->ver >= 20 && sfid == GFX12_SFID_UGM) {
const unsigned ex_mlen = brw_message_ex_desc_ex_mlen(devinfo, ex_desc_imm);
assert(ex_desc_imm == brw_message_ex_desc(devinfo, ex_mlen));
brw_SHR(p, addr, addr, brw_imm_ud(4));
} else {
/* Or the scratch surface offset together with the immediate part
* of the extended descriptor.
*/
brw_OR(p, addr, addr, brw_imm_ud(imm_part));
}
} else if (ex_desc.file == BRW_IMMEDIATE_VALUE) {
/* ex_desc bits 15:12 don't exist in the instruction encoding prior
* to Gfx12, so we may have fallen back to an indirect extended