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freedreno: Add missing foreach macros and update indentation

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Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10245>
This commit is contained in:
Rob Clark 2021-04-14 16:48:04 -07:00
parent 979ec228f2
commit b6a1e3a393
11 changed files with 64 additions and 90 deletions
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9
src/freedreno/.clang-format
View file

@ -54,6 +54,13 @@ ForEachMacros:
- nir_foreach_shader_out_variable_safe
- nir_foreach_variable_in_list
- nir_foreach_src
- nir_foreach_variable_with_modes_safe
- nir_foreach_variable_with_modes
- nir_foreach_shader_out_variable
- ir2_foreach_instr
- ir2_foreach_live_reg
- ir2_foreach_avail
- ir2_foreach_src
- foreach_two_lists
- foreach_bit
- foreach_sched_node
@ -80,6 +87,8 @@ ForEachMacros:
- foreach_name
- foreach_def
- foreach_use
- foreach_batch
- hash_table_foreach
- set_foreach
IncludeBlocks: Preserve

33
src/gallium/drivers/freedreno/a2xx/ir2.c
View file

@ -224,16 +224,14 @@ sched_next(struct ir2_context *ctx, struct ir2_sched_instr *sched)
int block_idx = -1;
/* XXX merge this loop with the other one somehow? */
ir2_foreach_instr(instr, ctx)
{
ir2_foreach_instr (instr, ctx) {
if (!instr->need_emit)
continue;
if (is_export(instr))
export = MIN2(export, export_buf(instr->alu.export));
}
ir2_foreach_instr(instr, ctx)
{
ir2_foreach_instr (instr, ctx) {
if (!instr->need_emit)
continue;
@ -254,8 +252,7 @@ sched_next(struct ir2_context *ctx, struct ir2_sched_instr *sched)
/* check if dependencies are satisfied */
bool is_ok = true;
ir2_foreach_src(src, instr)
{
ir2_foreach_src (src, instr) {
if (src->type == IR2_SRC_REG) {
/* need to check if all previous instructions in the block
* which write the reg have been emitted
@ -263,8 +260,7 @@ sched_next(struct ir2_context *ctx, struct ir2_sched_instr *sched)
* XXX: check components instead of whole register
*/
struct ir2_reg *reg = get_reg_src(ctx, src);
ir2_foreach_instr(p, ctx)
{
ir2_foreach_instr (p, ctx) {
if (!p->is_ssa && p->reg == reg && p->idx < instr->idx)
is_ok &= !p->need_emit;
}
@ -275,13 +271,11 @@ sched_next(struct ir2_context *ctx, struct ir2_sched_instr *sched)
}
/* don't reorder non-ssa write before read */
if (!instr->is_ssa) {
ir2_foreach_instr(p, ctx)
{
ir2_foreach_instr (p, ctx) {
if (!p->need_emit || p->idx >= instr->idx)
continue;
ir2_foreach_src(src, p)
{
ir2_foreach_src (src, p) {
if (get_reg_src(ctx, src) == instr->reg)
is_ok = false;
}
@ -303,8 +297,7 @@ sched_next(struct ir2_context *ctx, struct ir2_sched_instr *sched)
}
/* priority to FETCH instructions */
ir2_foreach_avail(instr)
{
ir2_foreach_avail (instr) {
if (instr->type == IR2_ALU)
continue;
@ -320,8 +313,7 @@ sched_next(struct ir2_context *ctx, struct ir2_sched_instr *sched)
/* TODO precompute priorities */
unsigned prio_v = ~0u, prio_s = ~0u, prio;
ir2_foreach_avail(instr)
{
ir2_foreach_avail (instr) {
prio = alu_vector_prio(instr);
if (prio < prio_v) {
instr_v = instr;
@ -331,8 +323,7 @@ sched_next(struct ir2_context *ctx, struct ir2_sched_instr *sched)
/* TODO can still insert scalar if src_count=3, if smart about it */
if (!instr_v || instr_v->src_count < 3) {
ir2_foreach_avail(instr)
{
ir2_foreach_avail (instr) {
bool compat = is_alu_compatible(instr_v, instr);
prio = alu_scalar_prio(instr);
@ -354,8 +345,7 @@ sched_next(struct ir2_context *ctx, struct ir2_sched_instr *sched)
* TODO: if we are smart we can still insert if instr_v->src_count==3
*/
if (!instr_s && instr_v->src_count < 3) {
ir2_foreach_avail(instr)
{
ir2_foreach_avail (instr) {
if (!is_alu_compatible(instr_v, instr) || !scalar_possible(instr))
continue;
@ -439,7 +429,8 @@ schedule_instrs(struct ir2_context *ctx)
}
bool free_block = true;
ir2_foreach_instr(instr, ctx) free_block &= instr->block_idx != block_idx;
ir2_foreach_instr (instr, ctx)
free_block &= instr->block_idx != block_idx;
if (free_block)
ra_block_free(ctx, block_idx);
};

21
src/gallium/drivers/freedreno/a2xx/ir2_cp.c
View file

@ -56,10 +56,8 @@ cp_src(struct ir2_context *ctx)
{
struct ir2_instr *p;
ir2_foreach_instr(instr, ctx)
{
ir2_foreach_src(src, instr)
{
ir2_foreach_instr (instr, ctx) {
ir2_foreach_src (src, instr) {
/* loop to replace recursively */
do {
if (src->type != IR2_SRC_SSA)
@ -107,8 +105,7 @@ cp_export(struct ir2_context *ctx)
struct ir2_reg *reg;
unsigned ncomp;
ir2_foreach_instr(instr, ctx)
{
ir2_foreach_instr (instr, ctx) {
if (!is_export(instr)) /* TODO */
continue;
@ -145,8 +142,7 @@ cp_export(struct ir2_context *ctx)
bool ok = true;
unsigned write_mask = 0;
ir2_foreach_instr(instr, ctx)
{
ir2_foreach_instr (instr, ctx) {
if (instr->is_ssa || instr->reg != reg)
continue;
@ -192,11 +188,11 @@ cp_export(struct ir2_context *ctx)
redirect &= (c[i]->block_idx == instr->block_idx);
/* no other instr using the value */
ir2_foreach_instr(p, ctx)
{
ir2_foreach_instr (p, ctx) {
if (p == instr)
continue;
ir2_foreach_src(src, p) redirect &= reg != get_reg_src(ctx, src);
ir2_foreach_src (src, p)
redirect &= reg != get_reg_src(ctx, src);
}
if (!redirect)
@ -223,7 +219,8 @@ cp_export(struct ir2_context *ctx)
default:
break;
}
ir2_foreach_src(s, p) swiz_merge_p(&s->swizzle, reswiz[i]);
ir2_foreach_src (s, p)
swiz_merge_p(&s->swizzle, reswiz[i]);
}
for (int i = 0; i < ncomp; i++) {

6
src/gallium/drivers/freedreno/a2xx/ir2_nir.c
View file

@ -132,8 +132,7 @@ ir2_optimize_nir(nir_shader *s, bool lower)
/* TODO we dont want to get shaders writing to depth for depth textures */
if (s->info.stage == MESA_SHADER_FRAGMENT) {
nir_foreach_shader_out_variable(var, s)
{
nir_foreach_shader_out_variable (var, s) {
if (var->data.location == FRAG_RESULT_DEPTH)
return -1;
}
@ -542,8 +541,7 @@ output_slot(struct ir2_context *ctx, nir_intrinsic_instr *intr)
{
int slot = -1;
unsigned idx = nir_intrinsic_base(intr);
nir_foreach_shader_out_variable(var, ctx->nir)
{
nir_foreach_shader_out_variable (var, ctx->nir) {
if (var->data.driver_location == idx) {
slot = var->data.location;
break;

21
src/gallium/drivers/freedreno/a2xx/ir2_ra.c
View file

@ -64,8 +64,7 @@ set_need_emit(struct ir2_context *ctx, struct ir2_instr *instr)
instr->need_emit = true;
ir2_foreach_src(src, instr)
{
ir2_foreach_src (src, instr) {
switch (src->type) {
case IR2_SRC_SSA:
set_need_emit(ctx, &ctx->instr[src->num]);
@ -73,8 +72,7 @@ set_need_emit(struct ir2_context *ctx, struct ir2_instr *instr)
case IR2_SRC_REG:
/* slow .. */
reg = get_reg_src(ctx, src);
ir2_foreach_instr(instr, ctx)
{
ir2_foreach_instr (instr, ctx) {
if (!instr->is_ssa && instr->reg == reg)
set_need_emit(ctx, instr);
}
@ -114,23 +112,20 @@ ra_count_refs(struct ir2_context *ctx)
/* mark instructions as needed
* need to do this because "substitutions" pass makes many movs not needed
*/
ir2_foreach_instr(instr, ctx)
{
ir2_foreach_instr (instr, ctx) {
if (has_side_effects(instr))
set_need_emit(ctx, instr);
}
/* compute ref_counts */
ir2_foreach_instr(instr, ctx)
{
ir2_foreach_instr (instr, ctx) {
/* kill non-needed so they can be skipped */
if (!instr->need_emit) {
instr->type = IR2_NONE;
continue;
}
ir2_foreach_src(src, instr)
{
ir2_foreach_src (src, instr) {
if (src->type == IR2_SRC_CONST)
continue;
@ -204,8 +199,7 @@ ra_src_free(struct ir2_context *ctx, struct ir2_instr *instr)
struct ir2_reg *reg;
struct ir2_reg_component *comp;
ir2_foreach_src(src, instr)
{
ir2_foreach_src (src, instr) {
if (src->type == IR2_SRC_CONST)
continue;
@ -226,8 +220,7 @@ ra_src_free(struct ir2_context *ctx, struct ir2_instr *instr)
void
ra_block_free(struct ir2_context *ctx, unsigned block)
{
ir2_foreach_live_reg(reg, ctx)
{
ir2_foreach_live_reg (reg, ctx) {
if (reg->block_idx_free != block)
continue;

12
src/gallium/drivers/freedreno/a6xx/fd6_texture.c
View file

@ -139,8 +139,7 @@ fd6_sampler_state_delete(struct pipe_context *pctx, void *hwcso)
fd_screen_lock(ctx->screen);
hash_table_foreach(fd6_ctx->tex_cache, entry)
{
hash_table_foreach (fd6_ctx->tex_cache, entry) {
struct fd6_texture_state *state = entry->data;
for (unsigned i = 0; i < ARRAY_SIZE(state->key.samp); i++) {
@ -348,8 +347,7 @@ fd6_sampler_view_destroy(struct pipe_context *pctx,
fd_screen_lock(ctx->screen);
hash_table_foreach(fd6_ctx->tex_cache, entry)
{
hash_table_foreach (fd6_ctx->tex_cache, entry) {
struct fd6_texture_state *state = entry->data;
for (unsigned i = 0; i < ARRAY_SIZE(state->key.view); i++) {
@ -478,8 +476,7 @@ fd6_rebind_resource(struct fd_context *ctx, struct fd_resource *rsc) assert_dt
struct fd6_context *fd6_ctx = fd6_context(ctx);
hash_table_foreach(fd6_ctx->tex_cache, entry)
{
hash_table_foreach (fd6_ctx->tex_cache, entry) {
struct fd6_texture_state *state = entry->data;
for (unsigned i = 0; i < ARRAY_SIZE(state->key.view); i++) {
@ -518,8 +515,7 @@ fd6_texture_fini(struct pipe_context *pctx)
fd_screen_lock(ctx->screen);
hash_table_foreach(fd6_ctx->tex_cache, entry)
{
hash_table_foreach (fd6_ctx->tex_cache, entry) {
remove_tex_entry(fd6_ctx, entry);
}

13
src/gallium/drivers/freedreno/freedreno_batch.c
View file

@ -230,8 +230,7 @@ batch_flush_dependencies(struct fd_batch *batch) assert_dt
struct fd_batch_cache *cache = &batch->ctx->screen->batch_cache;
struct fd_batch *dep;
foreach_batch(dep, cache, batch->dependents_mask)
{
foreach_batch (dep, cache, batch->dependents_mask) {
fd_batch_flush(dep);
fd_batch_reference(&dep, NULL);
}
@ -245,8 +244,7 @@ batch_reset_dependencies(struct fd_batch *batch)
struct fd_batch_cache *cache = &batch->ctx->screen->batch_cache;
struct fd_batch *dep;
foreach_batch(dep, cache, batch->dependents_mask)
{
foreach_batch (dep, cache, batch->dependents_mask) {
fd_batch_reference(&dep, NULL);
}
@ -407,8 +405,8 @@ recursive_dependents_mask(struct fd_batch *batch)
struct fd_batch *dep;
uint32_t dependents_mask = batch->dependents_mask;
foreach_batch(dep, cache, batch->dependents_mask) dependents_mask |=
recursive_dependents_mask(dep);
foreach_batch (dep, cache, batch->dependents_mask)
dependents_mask |= recursive_dependents_mask(dep);
return dependents_mask;
}
@ -489,8 +487,7 @@ fd_batch_resource_write(struct fd_batch *batch, struct fd_resource *rsc)
if (rsc->track->write_batch)
flush_write_batch(rsc);
foreach_batch(dep, cache, rsc->track->batch_mask)
{
foreach_batch (dep, cache, rsc->track->batch_mask) {
struct fd_batch *b = NULL;
if (dep == batch)
continue;

17
src/gallium/drivers/freedreno/freedreno_batch_cache.c
View file

@ -155,8 +155,7 @@ bc_flush(struct fd_batch_cache *cache, struct fd_context *ctx,
fd_screen_lock(ctx->screen);
foreach_batch(batch, cache, cache->batch_mask)
{
foreach_batch (batch, cache, cache->batch_mask) {
if (batch->ctx == ctx) {
fd_batch_reference_locked(&batches[n++], batch);
}
@ -210,7 +209,9 @@ batch_in_cache(struct fd_batch_cache *cache, struct fd_batch *batch)
{
struct fd_batch *b;
foreach_batch(b, cache, cache->batch_mask) if (b == batch) return true;
foreach_batch (b, cache, cache->batch_mask)
if (b == batch)
return true;
return false;
}
@ -250,8 +251,7 @@ fd_bc_invalidate_context(struct fd_context *ctx)
fd_screen_lock(ctx->screen);
foreach_batch(batch, cache, cache->batch_mask)
{
foreach_batch (batch, cache, cache->batch_mask) {
if (batch->ctx == ctx)
fd_bc_invalidate_batch(batch, true);
}
@ -311,8 +311,7 @@ fd_bc_invalidate_resource(struct fd_resource *rsc, bool destroy)
fd_screen_lock(screen);
if (destroy) {
foreach_batch(batch, &screen->batch_cache, rsc->track->batch_mask)
{
foreach_batch (batch, &screen->batch_cache, rsc->track->batch_mask) {
struct set_entry *entry = _mesa_set_search(batch->resources, rsc);
_mesa_set_remove(batch->resources, entry);
}
@ -321,7 +320,7 @@ fd_bc_invalidate_resource(struct fd_resource *rsc, bool destroy)
fd_batch_reference_locked(&rsc->track->write_batch, NULL);
}
foreach_batch(batch, &screen->batch_cache, rsc->track->bc_batch_mask)
foreach_batch (batch, &screen->batch_cache, rsc->track->bc_batch_mask)
fd_bc_invalidate_batch(batch, false);
rsc->track->bc_batch_mask = 0;
@ -343,7 +342,7 @@ alloc_batch_locked(struct fd_batch_cache *cache, struct fd_context *ctx,
for (unsigned i = 0; i < ARRAY_SIZE(cache->batches); i++) {
batch = cache->batches[i];
debug_printf("%d: needs_flush=%d, depends:", batch->idx, batch->needs_flush);
set_foreach(batch->dependencies, entry) {
set_foreach (batch->dependencies, entry) {
struct fd_batch *dep = (struct fd_batch *)entry->key;
debug_printf(" %d", dep->idx);
}

10
src/gallium/drivers/freedreno/freedreno_resource.c
View file

@ -389,8 +389,7 @@ fd_try_shadow_resource(struct fd_context *ctx, struct fd_resource *rsc,
*/
debug_assert(shadow->track->batch_mask == 0);
struct fd_batch *batch;
foreach_batch(batch, &ctx->screen->batch_cache, rsc->track->batch_mask)
{
foreach_batch (batch, &ctx->screen->batch_cache, rsc->track->batch_mask) {
struct set_entry *entry = _mesa_set_search(batch->resources, rsc);
_mesa_set_remove(batch->resources, entry);
_mesa_set_add(batch->resources, shadow);
@ -615,15 +614,14 @@ flush_resource(struct fd_context *ctx, struct fd_resource *rsc,
*/
fd_screen_lock(ctx->screen);
batch_mask = rsc->track->batch_mask;
foreach_batch(batch, &ctx->screen->batch_cache, batch_mask)
foreach_batch (batch, &ctx->screen->batch_cache, batch_mask)
fd_batch_reference_locked(&batches[batch->idx], batch);
fd_screen_unlock(ctx->screen);
foreach_batch(batch, &ctx->screen->batch_cache, batch_mask)
foreach_batch (batch, &ctx->screen->batch_cache, batch_mask)
fd_batch_flush(batch);
foreach_batch(batch, &ctx->screen->batch_cache, batch_mask)
{
foreach_batch (batch, &ctx->screen->batch_cache, batch_mask) {
fd_batch_reference(&batches[batch->idx], NULL);
}
assert(rsc->track->batch_mask == 0);

6
src/gallium/drivers/freedreno/ir3/ir3_cache.c
View file

@ -78,8 +78,7 @@ ir3_cache_destroy(struct ir3_cache *cache)
return;
/* _mesa_hash_table_destroy is so *almost* useful.. */
hash_table_foreach(cache->ht, entry)
{
hash_table_foreach (cache->ht, entry) {
cache->funcs->destroy_state(cache->data, entry->data);
}
@ -174,8 +173,7 @@ ir3_cache_invalidate(struct ir3_cache *cache, void *stobj)
if (!cache)
return;
hash_table_foreach(cache->ht, entry)
{
hash_table_foreach (cache->ht, entry) {
const struct ir3_cache_key *key = entry->key;
if ((key->fs == stobj) || (key->vs == stobj) || (key->ds == stobj) ||
(key->hs == stobj) || (key->gs == stobj)) {

6
src/gallium/drivers/freedreno/ir3/ir3_cmdline.c
View file

@ -82,8 +82,7 @@ sort_varyings(nir_shader *nir, nir_variable_mode mode)
{
struct exec_list new_list;
exec_list_make_empty(&new_list);
nir_foreach_variable_with_modes_safe(var, nir, mode)
{
nir_foreach_variable_with_modes_safe (var, nir, mode) {
exec_node_remove(&var->node);
insert_sorted(&new_list, var);
}
@ -93,8 +92,7 @@ sort_varyings(nir_shader *nir, nir_variable_mode mode)
static void
fixup_varying_slots(nir_shader *nir, nir_variable_mode mode)
{
nir_foreach_variable_with_modes(var, nir, mode)
{
nir_foreach_variable_with_modes (var, nir, mode) {
if (var->data.location >= VARYING_SLOT_VAR0) {
var->data.location += 9;
} else if ((var->data.location >= VARYING_SLOT_TEX0) &&