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freedreno: Manual fixups

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Things I couldn't figure out how to get clang-format to not mess up.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10245>
This commit is contained in:
Rob Clark 2021-02-05 13:42:42 -08:00
parent 3e337c947f
commit 979ec228f2
21 changed files with 130 additions and 148 deletions
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14
src/gallium/drivers/freedreno/a2xx/fd2_util.c
View file

@ -212,14 +212,12 @@ fd2_tex_swiz(enum pipe_format format, unsigned swizzle_r, unsigned swizzle_g,
unsigned swizzle_b, unsigned swizzle_a)
{
const struct util_format_description *desc = util_format_description(format);
unsigned char swiz[4] =
{
swizzle_r,
swizzle_g,
swizzle_b,
swizzle_a,
},
rswiz[4];
unsigned char swiz[4] = {
swizzle_r,
swizzle_g,
swizzle_b,
swizzle_a,
}, rswiz[4];
util_format_compose_swizzles(desc->swizzle, swiz, rswiz);

9
src/gallium/drivers/freedreno/a3xx/fd3_draw.c
View file

@ -106,11 +106,10 @@ fd3_draw_vbo(struct fd_context *ctx, const struct pipe_draw_info *info,
.info = info,
.indirect = indirect,
.draw = draw,
.key =
{
.vs = ctx->prog.vs,
.fs = ctx->prog.fs,
},
.key = {
.vs = ctx->prog.vs,
.fs = ctx->prog.fs,
},
.rasterflat = ctx->rasterizer->flatshade,
.sprite_coord_enable = ctx->rasterizer->sprite_coord_enable,
.sprite_coord_mode = ctx->rasterizer->sprite_coord_mode,

14
src/gallium/drivers/freedreno/a3xx/fd3_format.c
View file

@ -359,14 +359,12 @@ fd3_tex_swiz(enum pipe_format format, unsigned swizzle_r, unsigned swizzle_g,
unsigned swizzle_b, unsigned swizzle_a)
{
const struct util_format_description *desc = util_format_description(format);
unsigned char swiz[4] =
{
swizzle_r,
swizzle_g,
swizzle_b,
swizzle_a,
},
rswiz[4];
unsigned char swiz[4] = {
swizzle_r,
swizzle_g,
swizzle_b,
swizzle_a,
}, rswiz[4];
util_format_compose_swizzles(desc->swizzle, swiz, rswiz);

22
src/gallium/drivers/freedreno/a4xx/fd4_draw.c
View file

@ -84,19 +84,17 @@ fd4_draw_vbo(struct fd_context *ctx, const struct pipe_draw_info *info,
.info = info,
.indirect = indirect,
.draw = draw,
.key =
{
.vs = ctx->prog.vs,
.fs = ctx->prog.fs,
.key =
{
.rasterflat = ctx->rasterizer->flatshade,
.ucp_enables = ctx->rasterizer->clip_plane_enable,
.has_per_samp = fd4_ctx->fastc_srgb || fd4_ctx->vastc_srgb,
.vastc_srgb = fd4_ctx->vastc_srgb,
.fastc_srgb = fd4_ctx->fastc_srgb,
},
.key = {
.vs = ctx->prog.vs,
.fs = ctx->prog.fs,
.key = {
.rasterflat = ctx->rasterizer->flatshade,
.ucp_enables = ctx->rasterizer->clip_plane_enable,
.has_per_samp = fd4_ctx->fastc_srgb || fd4_ctx->vastc_srgb,
.vastc_srgb = fd4_ctx->vastc_srgb,
.fastc_srgb = fd4_ctx->fastc_srgb,
},
},
.rasterflat = ctx->rasterizer->flatshade,
.sprite_coord_enable = ctx->rasterizer->sprite_coord_enable,
.sprite_coord_mode = ctx->rasterizer->sprite_coord_mode,

14
src/gallium/drivers/freedreno/a4xx/fd4_format.c
View file

@ -408,14 +408,12 @@ fd4_tex_swiz(enum pipe_format format, unsigned swizzle_r, unsigned swizzle_g,
unsigned swizzle_b, unsigned swizzle_a)
{
const struct util_format_description *desc = util_format_description(format);
unsigned char swiz[4] =
{
swizzle_r,
swizzle_g,
swizzle_b,
swizzle_a,
},
rswiz[4];
unsigned char swiz[4] = {
swizzle_r,
swizzle_g,
swizzle_b,
swizzle_a,
}, rswiz[4];
util_format_compose_swizzles(desc->swizzle, swiz, rswiz);

15
src/gallium/drivers/freedreno/a5xx/fd5_blend.c
View file

@ -104,22 +104,21 @@ fd5_blend_state_create(struct pipe_context *pctx,
if (rt->blend_enable) {
so->rb_mrt[i].control |=
// A5XX_RB_MRT_CONTROL_READ_DEST_ENABLE
//|
A5XX_RB_MRT_CONTROL_BLEND | A5XX_RB_MRT_CONTROL_BLEND2;
// A5XX_RB_MRT_CONTROL_READ_DEST_ENABLE |
A5XX_RB_MRT_CONTROL_BLEND | A5XX_RB_MRT_CONTROL_BLEND2;
mrt_blend |= (1 << i);
so->lrz_write = false;
}
if (reads_dest) {
// so->rb_mrt[i].control |=
//A5XX_RB_MRT_CONTROL_READ_DEST_ENABLE;
// so->rb_mrt[i].control |=
// A5XX_RB_MRT_CONTROL_READ_DEST_ENABLE;
mrt_blend |= (1 << i);
}
// if (cso->dither)
// so->rb_mrt[i].buf_info |=
//A5XX_RB_MRT_BUF_INFO_DITHER_MODE(DITHER_ALWAYS);
// if (cso->dither)
// so->rb_mrt[i].buf_info |=
// A5XX_RB_MRT_BUF_INFO_DITHER_MODE(DITHER_ALWAYS);
}
so->rb_blend_cntl =

20
src/gallium/drivers/freedreno/a5xx/fd5_draw.c
View file

@ -80,18 +80,16 @@ fd5_draw_vbo(struct fd_context *ctx, const struct pipe_draw_info *info,
.info = info,
.indirect = indirect,
.draw = draw,
.key =
{
.vs = ctx->prog.vs,
.fs = ctx->prog.fs,
.key =
{
.rasterflat = ctx->rasterizer->flatshade,
.has_per_samp = fd5_ctx->fastc_srgb || fd5_ctx->vastc_srgb,
.vastc_srgb = fd5_ctx->vastc_srgb,
.fastc_srgb = fd5_ctx->fastc_srgb,
},
.key = {
.vs = ctx->prog.vs,
.fs = ctx->prog.fs,
.key = {
.rasterflat = ctx->rasterizer->flatshade,
.has_per_samp = fd5_ctx->fastc_srgb || fd5_ctx->vastc_srgb,
.vastc_srgb = fd5_ctx->vastc_srgb,
.fastc_srgb = fd5_ctx->fastc_srgb,
},
},
.rasterflat = ctx->rasterizer->flatshade,
.sprite_coord_enable = ctx->rasterizer->sprite_coord_enable,
.sprite_coord_mode = ctx->rasterizer->sprite_coord_mode,

14
src/gallium/drivers/freedreno/a5xx/fd5_format.c
View file

@ -411,14 +411,12 @@ fd5_tex_swiz(enum pipe_format format, unsigned swizzle_r, unsigned swizzle_g,
unsigned swizzle_b, unsigned swizzle_a)
{
const struct util_format_description *desc = util_format_description(format);
unsigned char swiz[4] =
{
swizzle_r,
swizzle_g,
swizzle_b,
swizzle_a,
},
rswiz[4];
unsigned char swiz[4] = {
swizzle_r,
swizzle_g,
swizzle_b,
swizzle_a,
}, rswiz[4];
util_format_compose_swizzles(desc->swizzle, swiz, rswiz);

7
src/gallium/drivers/freedreno/a5xx/fd5_rasterizer.c
View file

@ -86,9 +86,10 @@ fd5_rasterizer_state_create(struct pipe_context *pctx,
if (!cso->flatshade_first)
so->pc_primitive_cntl |= A5XX_PC_PRIMITIVE_CNTL_PROVOKING_VTX_LAST;
// if (!cso->depth_clip)
// so->gras_cl_clip_cntl |= A5XX_GRAS_CL_CLIP_CNTL_ZNEAR_CLIP_DISABLE
//| A5XX_GRAS_CL_CLIP_CNTL_ZFAR_CLIP_DISABLE;
// if (!cso->depth_clip)
// so->gras_cl_clip_cntl |=
// A5XX_GRAS_CL_CLIP_CNTL_ZNEAR_CLIP_DISABLE |
// A5XX_GRAS_CL_CLIP_CNTL_ZFAR_CLIP_DISABLE;
if (cso->clip_halfz)
so->gras_cl_clip_cntl |= A5XX_GRAS_CL_CNTL_ZERO_GB_SCALE_Z;

3
src/gallium/drivers/freedreno/a6xx/fd6_blend.c
View file

@ -131,8 +131,7 @@ __fd6_setup_blend_variant(struct fd6_blend_stateobj *blend,
.dual_color_in_enable =
blend->use_dual_src_blend, ));
OUT_REG(
ring,
OUT_REG(ring,
A6XX_RB_BLEND_CNTL(.enable_blend = mrt_blend,
.alpha_to_coverage = cso->alpha_to_coverage,
.alpha_to_one = cso->alpha_to_one,

29
src/gallium/drivers/freedreno/a6xx/fd6_blitter.c
View file

@ -288,12 +288,12 @@ emit_blit_setup(struct fd_ringbuffer *ring, enum pipe_format pfmt,
COND(util_format_is_pure_uint(pfmt), A6XX_SP_2D_DST_FORMAT_UINT) |
COND(util_format_is_snorm(pfmt),
A6XX_SP_2D_DST_FORMAT_SINT | A6XX_SP_2D_DST_FORMAT_NORM) |
COND(util_format_is_unorm(pfmt),
// TODO sometimes blob uses UINT+NORM but dEQP seems unhappy about
// that
// A6XX_SP_2D_DST_FORMAT_UINT
//|
A6XX_SP_2D_DST_FORMAT_NORM) |
COND(
util_format_is_unorm(pfmt),
// TODO sometimes blob uses UINT+NORM but dEQP seems unhappy about
// that
//A6XX_SP_2D_DST_FORMAT_UINT |
A6XX_SP_2D_DST_FORMAT_NORM) |
COND(is_srgb, A6XX_SP_2D_DST_FORMAT_SRGB) |
A6XX_SP_2D_DST_FORMAT_MASK(0xf));
@ -867,16 +867,15 @@ fd6_resolve_tile(struct fd_batch *batch, struct fd_ringbuffer *ring,
enum a3xx_msaa_samples samples = fd_msaa_samples(batch->framebuffer.samples);
OUT_PKT4(ring, REG_A6XX_SP_PS_2D_SRC_INFO, 10);
OUT_RING(
ring,
A6XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT(sfmt) |
A6XX_SP_PS_2D_SRC_INFO_TILE_MODE(TILE6_2) |
A6XX_SP_PS_2D_SRC_INFO_SAMPLES(samples) |
COND(samples > MSAA_ONE, A6XX_SP_PS_2D_SRC_INFO_SAMPLES_AVERAGE) |
COND(util_format_is_srgb(psurf->format), A6XX_SP_PS_2D_SRC_INFO_SRGB) |
A6XX_SP_PS_2D_SRC_INFO_UNK20 | A6XX_SP_PS_2D_SRC_INFO_UNK22);
OUT_RING(ring,
A6XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT(sfmt) |
A6XX_SP_PS_2D_SRC_INFO_TILE_MODE(TILE6_2) |
A6XX_SP_PS_2D_SRC_INFO_SAMPLES(samples) |
COND(samples > MSAA_ONE, A6XX_SP_PS_2D_SRC_INFO_SAMPLES_AVERAGE) |
COND(util_format_is_srgb(psurf->format), A6XX_SP_PS_2D_SRC_INFO_SRGB) |
A6XX_SP_PS_2D_SRC_INFO_UNK20 | A6XX_SP_PS_2D_SRC_INFO_UNK22);
OUT_RING(ring, A6XX_SP_PS_2D_SRC_SIZE_WIDTH(psurf->width) |
A6XX_SP_PS_2D_SRC_SIZE_HEIGHT(psurf->height));
A6XX_SP_PS_2D_SRC_SIZE_HEIGHT(psurf->height));
OUT_RING(ring, gmem_base); /* SP_PS_2D_SRC_LO */
OUT_RING(ring, gmem_base >> 32); /* SP_PS_2D_SRC_HI */
OUT_RING(ring, A6XX_SP_PS_2D_SRC_PITCH_PITCH(gmem_pitch));

9
src/gallium/drivers/freedreno/a6xx/fd6_compute.c
View file

@ -103,8 +103,7 @@ fd6_launch_grid(struct fd_context *ctx, const struct pipe_grid_info *info) in_dt
struct fd_ringbuffer *ring = ctx->batch->draw;
unsigned nglobal = 0;
v =
ir3_shader_variant(ir3_get_shader(ctx->compute), key, false, &ctx->debug);
v = ir3_shader_variant(ir3_get_shader(ctx->compute), key, false, &ctx->debug);
if (!v)
return;
@ -141,9 +140,9 @@ fd6_launch_grid(struct fd_context *ctx, const struct pipe_grid_info *info) in_dt
const unsigned work_dim = info->work_dim ? info->work_dim : 3;
OUT_PKT4(ring, REG_A6XX_HLSQ_CS_NDRANGE_0, 7);
OUT_RING(ring, A6XX_HLSQ_CS_NDRANGE_0_KERNELDIM(work_dim) |
A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX(local_size[0] - 1) |
A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY(local_size[1] - 1) |
A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ(local_size[2] - 1));
A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX(local_size[0] - 1) |
A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY(local_size[1] - 1) |
A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ(local_size[2] - 1));
OUT_RING(ring,
A6XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X(local_size[0] * num_groups[0]));
OUT_RING(ring, 0); /* HLSQ_CS_NDRANGE_2_GLOBALOFF_X */

23
src/gallium/drivers/freedreno/a6xx/fd6_draw.c
View file

@ -144,20 +144,17 @@ fd6_draw_vbo(struct fd_context *ctx, const struct pipe_draw_info *info,
.info = info,
.indirect = indirect,
.draw = draw,
.key =
{
.vs = ctx->prog.vs,
.gs = ctx->prog.gs,
.fs = ctx->prog.fs,
.key =
{
.rasterflat = ctx->rasterizer->flatshade,
.layer_zero = !gs_info ||
!(gs_info->outputs_written & VARYING_BIT_LAYER),
.sample_shading = (ctx->min_samples > 1),
.msaa = (ctx->framebuffer.samples > 1),
},
.key = {
.vs = ctx->prog.vs,
.gs = ctx->prog.gs,
.fs = ctx->prog.fs,
.key = {
.rasterflat = ctx->rasterizer->flatshade,
.layer_zero = !gs_info || !(gs_info->outputs_written & VARYING_BIT_LAYER),
.sample_shading = (ctx->min_samples > 1),
.msaa = (ctx->framebuffer.samples > 1),
},
},
.rasterflat = ctx->rasterizer->flatshade,
.sprite_coord_enable = ctx->rasterizer->sprite_coord_enable,
.sprite_coord_mode = ctx->rasterizer->sprite_coord_mode,

12
src/gallium/drivers/freedreno/a6xx/fd6_vsc.c
View file

@ -151,12 +151,12 @@ fd6_vsc_update_sizes(struct fd_batch *batch, const struct pipe_draw_info *info,
draw_stream_size_bits(info, batch->num_bins_per_pipe, prim_strm_bits);
#if 0
printf("vsc: prim_strm_bits=%d, draw_strm_bits=%d, nb=%u, ic=%u, c=%u, pc=%u (%s)\n",
prim_strm_bits, draw_strm_bits, batch->num_bins_per_pipe,
info->instance_count, info->count,
(info->count * info->instance_count) /
u_vertices_per_prim(info->mode),
u_prim_name(info->mode));
printf("vsc: prim_strm_bits=%d, draw_strm_bits=%d, nb=%u, ic=%u, c=%u, pc=%u (%s)\n",
prim_strm_bits, draw_strm_bits, batch->num_bins_per_pipe,
info->instance_count, info->count,
(info->count * info->instance_count) /
u_vertices_per_prim(info->mode),
u_prim_name(info->mode));
#endif
batch->prim_strm_bits += prim_strm_bits;

3
src/gallium/drivers/freedreno/freedreno_batch.h
View file

@ -90,8 +90,7 @@ struct fd_batch {
FD_BUFFER_DEPTH = PIPE_CLEAR_DEPTH,
FD_BUFFER_STENCIL = PIPE_CLEAR_STENCIL,
FD_BUFFER_ALL = FD_BUFFER_COLOR | FD_BUFFER_DEPTH | FD_BUFFER_STENCIL,
} invalidated,
cleared, fast_cleared, restore, resolve;
} invalidated, cleared, fast_cleared, restore, resolve;
/* is this a non-draw batch (ie compute/blit which has no pfb state)? */
bool nondraw : 1;

18
src/gallium/drivers/freedreno/freedreno_batch_cache.c
View file

@ -340,15 +340,15 @@ alloc_batch_locked(struct fd_batch_cache *cache, struct fd_context *ctx,
while ((idx = ffs(~cache->batch_mask)) == 0) {
#if 0
for (unsigned i = 0; i < ARRAY_SIZE(cache->batches); i++) {
batch = cache->batches[i];
debug_printf("%d: needs_flush=%d, depends:", batch->idx, batch->needs_flush);
set_foreach(batch->dependencies, entry) {
struct fd_batch *dep = (struct fd_batch *)entry->key;
debug_printf(" %d", dep->idx);
}
debug_printf("\n");
}
for (unsigned i = 0; i < ARRAY_SIZE(cache->batches); i++) {
batch = cache->batches[i];
debug_printf("%d: needs_flush=%d, depends:", batch->idx, batch->needs_flush);
set_foreach(batch->dependencies, entry) {
struct fd_batch *dep = (struct fd_batch *)entry->key;
debug_printf(" %d", dep->idx);
}
debug_printf("\n");
}
#endif
/* TODO: is LRU the better policy? Or perhaps the batch that
* depends on the fewest other batches?

4
src/gallium/drivers/freedreno/freedreno_context.c
View file

@ -167,8 +167,10 @@ fd_memory_barrier(struct pipe_context *pctx, unsigned flags)
return;
fd_context_flush(pctx, NULL, 0);
/* TODO do we need to check for persistently mapped buffers and
* fd_bo_cpu_prep()?? */
* fd_bo_cpu_prep()??
*/
}
static void

6
src/gallium/drivers/freedreno/freedreno_gmem.c
View file

@ -92,8 +92,7 @@
struct gmem_key {
uint16_t minx, miny;
uint16_t width, height;
uint8_t
gmem_page_align; /* alignment in multiples of 0x1000 to reduce key size */
uint8_t gmem_page_align; /* alignment in multiples of 0x1000 to reduce key size */
uint8_t nr_cbufs;
uint8_t cbuf_cpp[MAX_RENDER_TARGETS];
uint8_t zsbuf_cpp[2];
@ -460,8 +459,7 @@ gmem_key_init(struct fd_batch *batch, bool assume_zs, bool no_scis_opt)
{
struct fd_screen *screen = batch->ctx->screen;
struct pipe_framebuffer_state *pfb = &batch->framebuffer;
bool has_zs =
pfb->zsbuf &&
bool has_zs = pfb->zsbuf &&
!!(batch->gmem_reason & (FD_GMEM_DEPTH_ENABLED | FD_GMEM_STENCIL_ENABLED |
FD_GMEM_CLEARS_DEPTH_STENCIL));
struct gmem_key *key = rzalloc(screen->gmem_cache.ht, struct gmem_key);

3
src/gallium/drivers/freedreno/freedreno_query.c
View file

@ -105,8 +105,7 @@ fd_render_condition(struct pipe_context *pctx, struct pipe_query *pq,
ctx->cond_mode = mode;
}
#define _Q(_name, _query_type, _type, _result_type) \
{ \
#define _Q(_name, _query_type, _type, _result_type) { \
.name = _name, .query_type = _query_type, \
.type = PIPE_DRIVER_QUERY_TYPE_##_type, \
.result_type = PIPE_DRIVER_QUERY_RESULT_TYPE_##_result_type, \

13
src/gallium/drivers/freedreno/gmemtool.c
View file

@ -94,14 +94,17 @@ struct gpu_info {
/* keep sorted by gpu name: */
static const struct gpu_info gpu_infos[] = {
{"a306", 307, 4, SZ_128K}, {"a405", 405, 4, SZ_256K},
{"a530", 530, 4, SZ_1M}, {"a618", 618, 1, SZ_512K},
{"a630", 630, 1, SZ_1M}, {"a650", 630, 1, SZ_1M + SZ_128K},
{"a306", 307, 4, SZ_128K},
{"a405", 405, 4, SZ_256K},
{"a530", 530, 4, SZ_1M},
{"a618", 618, 1, SZ_512K},
{"a630", 630, 1, SZ_1M},
{"a650", 630, 1, SZ_1M + SZ_128K},
};
static const struct option opts[] = {
{.name = "gpu", .has_arg = 1, NULL, 'g'},
{.name = "help", .has_arg = 0, NULL, 'h'},
{.name = "gpu", .has_arg = 1, NULL, 'g'},
{.name = "help", .has_arg = 0, NULL, 'h'},
{.name = "verbose", .has_arg = 0, NULL, 'v'},
{}};

26
src/gallium/drivers/freedreno/ir3/ir3_cmdline.c
View file

@ -231,18 +231,18 @@ load_spirv(const char *filename, const char *entry, gl_shader_stage stage)
{
const struct spirv_to_nir_options spirv_options = {
/* these caps are just make-believe */
.caps =
{
.draw_parameters = true,
.float64 = true,
.image_read_without_format = true,
.image_write_without_format = true,
.int64 = true,
.variable_pointers = true,
},
.caps = {
.draw_parameters = true,
.float64 = true,
.image_read_without_format = true,
.image_write_without_format = true,
.int64 = true,
.variable_pointers = true,
},
.debug = {
.func = debug_func,
}};
}
};
nir_shader *nir;
void *buf;
size_t size;
@ -261,9 +261,9 @@ load_spirv(const char *filename, const char *entry, gl_shader_stage stage)
static const char *shortopts = "g:hv";
static const struct option longopts[] = {
{"gpu", required_argument, 0, 'g'},
{"help", no_argument, 0, 'h'},
{"verbose", no_argument, 0, 'v'},
{"gpu", required_argument, 0, 'g'},
{"help", no_argument, 0, 'h'},
{"verbose", no_argument, 0, 'v'},
};
static void