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intel/dev: Adjust prefetch_size values for Xe2 engines

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Xe2 follows MTL and has different prefetch sizes for different
types of engines.

BSpec: 60223
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26396>
This commit is contained in:
José Roberto de Souza 2023-11-28 10:05:50 -08:00 • committed by Marge Bot
parent 046cc51223
commit b27ca68143
1 changed files with 16 additions and 3 deletions
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19
src/intel/dev/intel_device_info.c
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@ -1555,8 +1555,16 @@ static unsigned
intel_device_info_calc_engine_prefetch(const struct intel_device_info *devinfo,
enum intel_engine_class engine_class)
{
if (devinfo->verx10 < 125)
return 512;
if (devinfo->verx10 >= 200) {
switch (engine_class) {
case INTEL_ENGINE_CLASS_RENDER:
return 4096;
case INTEL_ENGINE_CLASS_COMPUTE:
return 1024;
default:
return 512;
}
}
if (intel_device_info_is_mtl(devinfo)) {
switch (engine_class) {
@ -1569,7 +1577,12 @@ intel_device_info_calc_engine_prefetch(const struct intel_device_info *devinfo,
}
}
return 1024;
/* DG2 */
if (devinfo->verx10 == 125)
return 1024;
/* Older than DG2/MTL */
return 512;
}
bool