From b27ca68143fe77185a2b5801029fec8ad7a59cdb Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Jos=C3=A9=20Roberto=20de=20Souza?= <jose.souza@intel.com>
Date: Tue, 28 Nov 2023 10:05:50 -0800
Subject: [PATCH] intel/dev: Adjust prefetch_size values for Xe2 engines
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Xe2 follows MTL and has different prefetch sizes for different
types of engines.

BSpec: 60223
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26396>
---
 src/intel/dev/intel_device_info.c | 19 ++++++++++++++++---
 1 file changed, 16 insertions(+), 3 deletions(-)

diff --git a/src/intel/dev/intel_device_info.c b/src/intel/dev/intel_device_info.c
index 61f04dbaa03..2da815e46d1 100644
--- a/src/intel/dev/intel_device_info.c
+++ b/src/intel/dev/intel_device_info.c
@@ -1555,8 +1555,16 @@ static unsigned
 intel_device_info_calc_engine_prefetch(const struct intel_device_info *devinfo,
                                        enum intel_engine_class engine_class)
 {
-   if (devinfo->verx10 < 125)
-      return 512;
+   if (devinfo->verx10 >= 200) {
+      switch (engine_class) {
+      case INTEL_ENGINE_CLASS_RENDER:
+         return 4096;
+      case INTEL_ENGINE_CLASS_COMPUTE:
+         return 1024;
+      default:
+         return 512;
+      }
+   }
 
    if (intel_device_info_is_mtl(devinfo)) {
       switch (engine_class) {
@@ -1569,7 +1577,12 @@ intel_device_info_calc_engine_prefetch(const struct intel_device_info *devinfo,
       }
    }
 
-   return 1024;
+   /* DG2 */
+   if (devinfo->verx10 == 125)
+      return 1024;
+
+   /* Older than DG2/MTL */
+   return 512;
 }
 
 bool