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ac/gpu_info: reorder the fields and print them nicely
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parent
a0a96819e1
commit
b1f33086ec
2 changed files with 74 additions and 53 deletions
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@ -404,54 +404,69 @@ void ac_compute_device_uuid(struct radeon_info *info, char *uuid, size_t size)
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void ac_print_gpu_info(struct radeon_info *info)
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{
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printf("pci (domain:bus:dev.func): %04x:%02x:%02x.%x\n",
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printf("Device info:\n");
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printf(" pci (domain:bus:dev.func): %04x:%02x:%02x.%x\n",
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info->pci_domain, info->pci_bus,
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info->pci_dev, info->pci_func);
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printf("pci_id = 0x%x\n", info->pci_id);
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printf("family = %i\n", info->family);
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printf("chip_class = %i\n", info->chip_class);
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printf("pte_fragment_size = %u\n", info->pte_fragment_size);
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printf("gart_page_size = %u\n", info->gart_page_size);
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printf("gart_size = %i MB\n", (int)DIV_ROUND_UP(info->gart_size, 1024*1024));
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printf("vram_size = %i MB\n", (int)DIV_ROUND_UP(info->vram_size, 1024*1024));
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printf("vram_vis_size = %i MB\n", (int)DIV_ROUND_UP(info->vram_vis_size, 1024*1024));
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printf("gds_size = %u kB\n", info->gds_size / 1024);
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printf("gds_gfx_partition_size = %u kB\n", info->gds_gfx_partition_size / 1024);
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printf("max_alloc_size = %i MB\n",
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printf(" pci_id = 0x%x\n", info->pci_id);
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printf(" family = %i\n", info->family);
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printf(" chip_class = %i\n", info->chip_class);
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printf(" num_compute_rings = %u\n", info->num_compute_rings);
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printf(" num_sdma_rings = %i\n", info->num_sdma_rings);
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printf(" clock_crystal_freq = %i\n", info->clock_crystal_freq);
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printf(" tcc_cache_line_size = %u\n", info->tcc_cache_line_size);
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printf("Memory info:\n");
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printf(" pte_fragment_size = %u\n", info->pte_fragment_size);
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printf(" gart_page_size = %u\n", info->gart_page_size);
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printf(" gart_size = %i MB\n", (int)DIV_ROUND_UP(info->gart_size, 1024*1024));
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printf(" vram_size = %i MB\n", (int)DIV_ROUND_UP(info->vram_size, 1024*1024));
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printf(" vram_vis_size = %i MB\n", (int)DIV_ROUND_UP(info->vram_vis_size, 1024*1024));
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printf(" gds_size = %u kB\n", info->gds_size / 1024);
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printf(" gds_gfx_partition_size = %u kB\n", info->gds_gfx_partition_size / 1024);
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printf(" max_alloc_size = %i MB\n",
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(int)DIV_ROUND_UP(info->max_alloc_size, 1024*1024));
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printf("min_alloc_size = %u\n", info->min_alloc_size);
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printf("address32_hi = %u\n", info->address32_hi);
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printf("has_dedicated_vram = %u\n", info->has_dedicated_vram);
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printf("gfx_ib_pad_with_type2 = %i\n", info->gfx_ib_pad_with_type2);
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printf("has_hw_decode = %u\n", info->has_hw_decode);
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printf("ib_start_alignment = %u\n", info->ib_start_alignment);
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printf("num_sdma_rings = %i\n", info->num_sdma_rings);
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printf("num_compute_rings = %u\n", info->num_compute_rings);
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printf("uvd_fw_version = %u\n", info->uvd_fw_version);
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printf("vce_fw_version = %u\n", info->vce_fw_version);
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printf("me_fw_version = %i\n", info->me_fw_version);
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printf("me_fw_feature = %i\n", info->me_fw_feature);
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printf("pfp_fw_version = %i\n", info->pfp_fw_version);
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printf("pfp_fw_feature = %i\n", info->pfp_fw_feature);
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printf("ce_fw_version = %i\n", info->ce_fw_version);
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printf("ce_fw_feature = %i\n", info->ce_fw_feature);
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printf("vce_harvest_config = %i\n", info->vce_harvest_config);
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printf("clock_crystal_freq = %i\n", info->clock_crystal_freq);
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printf("tcc_cache_line_size = %u\n", info->tcc_cache_line_size);
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printf("drm = %i.%i.%i\n", info->drm_major,
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printf(" min_alloc_size = %u\n", info->min_alloc_size);
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printf(" address32_hi = %u\n", info->address32_hi);
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printf(" has_dedicated_vram = %u\n", info->has_dedicated_vram);
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printf("CP info:\n");
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printf(" gfx_ib_pad_with_type2 = %i\n", info->gfx_ib_pad_with_type2);
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printf(" ib_start_alignment = %u\n", info->ib_start_alignment);
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printf(" me_fw_version = %i\n", info->me_fw_version);
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printf(" me_fw_feature = %i\n", info->me_fw_feature);
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printf(" pfp_fw_version = %i\n", info->pfp_fw_version);
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printf(" pfp_fw_feature = %i\n", info->pfp_fw_feature);
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printf(" ce_fw_version = %i\n", info->ce_fw_version);
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printf(" ce_fw_feature = %i\n", info->ce_fw_feature);
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printf("Multimedia info:\n");
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printf(" has_hw_decode = %u\n", info->has_hw_decode);
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printf(" uvd_enc_supported = %u\n", info->uvd_enc_supported);
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printf(" uvd_fw_version = %u\n", info->uvd_fw_version);
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printf(" vce_fw_version = %u\n", info->vce_fw_version);
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printf(" vce_harvest_config = %i\n", info->vce_harvest_config);
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printf("Kernel info:\n");
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printf(" drm = %i.%i.%i\n", info->drm_major,
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info->drm_minor, info->drm_patchlevel);
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printf("has_userptr = %i\n", info->has_userptr);
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printf("has_syncobj = %u\n", info->has_syncobj);
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printf("has_fence_to_handle = %u\n", info->has_fence_to_handle);
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printf(" has_userptr = %i\n", info->has_userptr);
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printf(" has_syncobj = %u\n", info->has_syncobj);
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printf(" has_syncobj_wait_for_submit = %u\n", info->has_syncobj_wait_for_submit);
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printf(" has_fence_to_handle = %u\n", info->has_fence_to_handle);
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printf(" has_ctx_priority = %u\n", info->has_ctx_priority);
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printf(" has_local_buffers = %u\n", info->has_local_buffers);
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printf("max_shader_clock = %i\n", info->max_shader_clock);
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printf("num_good_compute_units = %i\n", info->num_good_compute_units);
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printf("max_se = %i\n", info->max_se);
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printf("max_sh_per_se = %i\n", info->max_sh_per_se);
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printf("Shader core info:\n");
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printf(" max_shader_clock = %i\n", info->max_shader_clock);
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printf(" num_good_compute_units = %i\n", info->num_good_compute_units);
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printf(" max_se = %i\n", info->max_se);
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printf(" max_sh_per_se = %i\n", info->max_sh_per_se);
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printf("num_render_backends = %i\n", info->num_render_backends);
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printf("num_tile_pipes = %i\n", info->num_tile_pipes);
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printf("pipe_interleave_bytes = %i\n", info->pipe_interleave_bytes);
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printf("enabled_rb_mask = 0x%x\n", info->enabled_rb_mask);
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printf("max_alignment = %u\n", (unsigned)info->max_alignment);
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printf("Render backend info:\n");
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printf(" num_render_backends = %i\n", info->num_render_backends);
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printf(" num_tile_pipes = %i\n", info->num_tile_pipes);
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printf(" pipe_interleave_bytes = %i\n", info->pipe_interleave_bytes);
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printf(" enabled_rb_mask = 0x%x\n", info->enabled_rb_mask);
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printf(" max_alignment = %u\n", (unsigned)info->max_alignment);
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}
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@ -50,6 +50,12 @@ struct radeon_info {
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uint32_t pci_id;
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enum radeon_family family;
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enum chip_class chip_class;
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uint32_t num_compute_rings;
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uint32_t num_sdma_rings;
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uint32_t clock_crystal_freq;
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uint32_t tcc_cache_line_size;
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/* Memory info. */
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uint32_t pte_fragment_size;
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uint32_t gart_page_size;
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uint64_t gart_size;
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@ -62,23 +68,23 @@ struct radeon_info {
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uint32_t address32_hi;
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bool has_dedicated_vram;
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bool r600_has_virtual_memory;
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/* CP info. */
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bool gfx_ib_pad_with_type2;
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bool has_hw_decode;
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unsigned ib_start_alignment;
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uint32_t num_sdma_rings;
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uint32_t num_compute_rings;
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uint32_t uvd_fw_version;
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uint32_t vce_fw_version;
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bool uvd_enc_supported;
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uint32_t me_fw_version;
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uint32_t me_fw_feature;
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uint32_t pfp_fw_version;
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uint32_t pfp_fw_feature;
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uint32_t ce_fw_version;
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uint32_t ce_fw_feature;
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/* Multimedia info. */
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bool has_hw_decode;
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bool uvd_enc_supported;
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uint32_t uvd_fw_version;
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uint32_t vce_fw_version;
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uint32_t vce_harvest_config;
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uint32_t clock_crystal_freq;
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uint32_t tcc_cache_line_size;
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/* Kernel info. */
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uint32_t drm_major; /* version */
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@ -108,8 +114,8 @@ struct radeon_info {
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uint32_t num_tile_pipes; /* pipe count from PIPE_CONFIG */
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uint32_t pipe_interleave_bytes;
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uint32_t enabled_rb_mask; /* GCN harvest config */
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uint64_t max_alignment; /* from addrlib */
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/* Tile modes. */
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uint32_t si_tile_mode_array[32];
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uint32_t cik_macrotile_mode_array[16];
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