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nir/divergence: Consider ttmp_register_amd and load_scalar_arg_amd as workgroup divergent

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These are SGPR inputs, so they are uniform in subgroups but may
have different values in different subgroups.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41584>
This commit is contained in:
Timur Kristóf 2026-05-14 21:15:00 +02:00 • committed by Marge Bot
parent dd5b6f3940
commit b0b61a4bf8
1 changed files with 2 additions and 2 deletions
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4
src/compiler/nir/nir_divergence_analysis.c
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@ -199,6 +199,8 @@ visit_intrinsic(nir_intrinsic_instr *instr, struct divergence_state *state)
case nir_intrinsic_load_sm_id_nv:
case nir_intrinsic_load_warp_id_nv:
case nir_intrinsic_load_warp_id_arm:
case nir_intrinsic_load_ttmp_register_amd:
case nir_intrinsic_load_scalar_arg_amd:
/* VS/TES/GS invocations of the same primitive can be in different
* subgroups, so subgroup ops are always divergent between vertices of
* the same primitive.
@ -311,8 +313,6 @@ visit_intrinsic(nir_intrinsic_instr *instr, struct divergence_state *state)
case nir_intrinsic_load_force_vrs_rates_amd:
case nir_intrinsic_load_tess_level_inner_default:
case nir_intrinsic_load_tess_level_outer_default:
case nir_intrinsic_load_ttmp_register_amd:
case nir_intrinsic_load_scalar_arg_amd:
case nir_intrinsic_load_resume_shader_address_amd:
case nir_intrinsic_load_reloc_const_intel:
case nir_intrinsic_load_btd_global_arg_addr_intel: