From b0b61a4bf8a270eabaefc28164c129d0a99557fd Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Timur=20Krist=C3=B3f?= Date: Thu, 14 May 2026 21:15:00 +0200 Subject: [PATCH] nir/divergence: Consider ttmp_register_amd and load_scalar_arg_amd as workgroup divergent MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit These are SGPR inputs, so they are uniform in subgroups but may have different values in different subgroups. Signed-off-by: Timur Kristóf Reviewed-by: Daniel Schürmann Reviewed-by: Georg Lehmann Part-of: --- src/compiler/nir/nir_divergence_analysis.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/compiler/nir/nir_divergence_analysis.c b/src/compiler/nir/nir_divergence_analysis.c index a7e485d869c..f658e65ed87 100644 --- a/src/compiler/nir/nir_divergence_analysis.c +++ b/src/compiler/nir/nir_divergence_analysis.c @@ -199,6 +199,8 @@ visit_intrinsic(nir_intrinsic_instr *instr, struct divergence_state *state) case nir_intrinsic_load_sm_id_nv: case nir_intrinsic_load_warp_id_nv: case nir_intrinsic_load_warp_id_arm: + case nir_intrinsic_load_ttmp_register_amd: + case nir_intrinsic_load_scalar_arg_amd: /* VS/TES/GS invocations of the same primitive can be in different * subgroups, so subgroup ops are always divergent between vertices of * the same primitive. @@ -311,8 +313,6 @@ visit_intrinsic(nir_intrinsic_instr *instr, struct divergence_state *state) case nir_intrinsic_load_force_vrs_rates_amd: case nir_intrinsic_load_tess_level_inner_default: case nir_intrinsic_load_tess_level_outer_default: - case nir_intrinsic_load_ttmp_register_amd: - case nir_intrinsic_load_scalar_arg_amd: case nir_intrinsic_load_resume_shader_address_amd: case nir_intrinsic_load_reloc_const_intel: case nir_intrinsic_load_btd_global_arg_addr_intel: