diff --git a/src/etnaviv/hw/state_3d.xml.h b/src/etnaviv/hw/state_3d.xml.h index c04e4b3657a..0a1c2af72eb 100644 --- a/src/etnaviv/hw/state_3d.xml.h +++ b/src/etnaviv/hw/state_3d.xml.h @@ -14,7 +14,7 @@ The rules-ng-ng source files this header was generated from are: - state_hi.xml ( 35909 bytes, from 2024-12-05 12:09:36) - copyright.xml ( 1597 bytes, from 2020-10-28 12:56:03) - state_2d.xml ( 52271 bytes, from 2023-05-30 20:50:02) -- state_3d.xml ( 89428 bytes, from 2025-03-14 21:09:00) +- state_3d.xml ( 89609 bytes, from 2025-07-13 22:31:44) - state_blt.xml ( 14592 bytes, from 2024-12-05 12:09:36) - state_vg.xml ( 5975 bytes, from 2020-10-28 12:56:03) @@ -257,18 +257,8 @@ DEALINGS IN THE SOFTWARE. #define VIVS_VS_RANGE_HIGH__SHIFT 16 #define VIVS_VS_RANGE_HIGH(x) (((x) << VIVS_VS_RANGE_HIGH__SHIFT) & VIVS_VS_RANGE_HIGH__MASK) -#define VIVS_VS_UNIFORM_CACHE 0x00000860 -#define VIVS_VS_UNIFORM_CACHE_FLUSH 0x00000001 -#define VIVS_VS_UNIFORM_CACHE_PS 0x00000010 -#define VIVS_VS_UNIFORM_CACHE_RTNE_ROUNDING 0x00001000 - #define VIVS_VS_UNIFORM_BASE 0x00000864 -#define VIVS_VS_ICACHE_CONTROL 0x00000868 -#define VIVS_VS_ICACHE_CONTROL_ENABLE 0x00000001 -#define VIVS_VS_ICACHE_CONTROL_FLUSH_VS 0x00000010 -#define VIVS_VS_ICACHE_CONTROL_FLUSH_PS 0x00000020 - #define VIVS_VS_INST_ADDR 0x0000086c #define VIVS_VS_HALTI5_OUTPUT_COUNT 0x00000870 @@ -281,9 +271,7 @@ DEALINGS IN THE SOFTWARE. #define VIVS_VS_NEWRANGE_LOW 0x00000874 -#define VIVS_VS_HALTI5_UNK00878 0x00000878 - -#define VIVS_VS_HALTI5_UNK00880 0x00000880 +#define VIVS_VS_NEWRANGE_HIGH 0x00000878 #define VIVS_VS_HALTI1_UNK00884 0x00000884 @@ -317,7 +305,7 @@ DEALINGS IN THE SOFTWARE. #define VIVS_VS_HALTI5_UNK008B8 0x000008b8 -#define VIVS_VS_NEWRANGE_HIGH 0x000008bc +#define VIVS_VS_HALTI5_RANGE_HIGH 0x000008bc #define VIVS_VS_HALTI5_INPUT(i0) (0x000008c0 + 0x4*(i0)) #define VIVS_VS_HALTI5_INPUT__ESIZE 0x00000004 @@ -744,7 +732,9 @@ DEALINGS IN THE SOFTWARE. #define VIVS_PS_NEWRANGE_LOW 0x0000087c -#define VIVS_PS_NEWRANGE_HIGH 0x00001090 +#define VIVS_PS_NEWRANGE_HIGH 0x00000880 + +#define VIVS_PS_HALTI5_RANGE_HIGH 0x00001090 #define VIVS_PS_ICACHE_COUNT 0x00001094 @@ -1976,6 +1966,16 @@ DEALINGS IN THE SOFTWARE. #define VIVS_SH 0x00000000 +#define VIVS_SH_CONTROL 0x00000860 +#define VIVS_SH_CONTROL_PS_CODE 0x00000001 +#define VIVS_SH_CONTROL_PS_UNIFORM 0x00000010 +#define VIVS_SH_CONTROL_RTNE_ROUNDING 0x00001000 + +#define VIVS_SH_ICACHE_CONTROL 0x00000868 +#define VIVS_SH_ICACHE_CONTROL_ENABLE 0x00000001 +#define VIVS_SH_ICACHE_CONTROL_FLUSH_VS 0x00000010 +#define VIVS_SH_ICACHE_CONTROL_FLUSH_PS 0x00000020 + #define VIVS_SH_CONFIG 0x00015600 #define VIVS_SH_CONFIG_RTNE_ROUNDING 0x00000002 #define VIVS_SH_CONFIG_DUAL16 0x00000004 diff --git a/src/gallium/drivers/etnaviv/etnaviv_emit.c b/src/gallium/drivers/etnaviv/etnaviv_emit.c index 9e741ac3bf2..bb855d08076 100644 --- a/src/gallium/drivers/etnaviv/etnaviv_emit.c +++ b/src/gallium/drivers/etnaviv/etnaviv_emit.c @@ -652,20 +652,20 @@ etna_emit_state(struct etna_context *ctx) assert(ctx->shader_state.VS_INST_ADDR.bo && ctx->shader_state.PS_INST_ADDR.bo); /* Set icache (VS) */ etna_set_state(stream, VIVS_VS_NEWRANGE_LOW, 0); - etna_set_state(stream, VIVS_VS_NEWRANGE_HIGH, ctx->shader_state.vs_inst_mem_size / 4); + etna_set_state(stream, VIVS_VS_HALTI5_RANGE_HIGH, ctx->shader_state.vs_inst_mem_size / 4); assert(ctx->shader_state.VS_INST_ADDR.bo); etna_set_state_reloc(stream, VIVS_VS_INST_ADDR, &ctx->shader_state.VS_INST_ADDR); etna_set_state(stream, VIVS_SH_CONFIG, 0x00000002); - etna_set_state(stream, VIVS_VS_ICACHE_CONTROL, VIVS_VS_ICACHE_CONTROL_ENABLE); + etna_set_state(stream, VIVS_SH_ICACHE_CONTROL, VIVS_SH_ICACHE_CONTROL_ENABLE); etna_set_state(stream, VIVS_VS_ICACHE_COUNT, ctx->shader_state.vs_inst_mem_size / 4 - 1); /* Set icache (PS) */ etna_set_state(stream, VIVS_PS_NEWRANGE_LOW, 0); - etna_set_state(stream, VIVS_PS_NEWRANGE_HIGH, ctx->shader_state.ps_inst_mem_size / 4); + etna_set_state(stream, VIVS_PS_HALTI5_RANGE_HIGH, ctx->shader_state.ps_inst_mem_size / 4); assert(ctx->shader_state.PS_INST_ADDR.bo); etna_set_state_reloc(stream, VIVS_PS_INST_ADDR, &ctx->shader_state.PS_INST_ADDR); etna_set_state(stream, VIVS_SH_CONFIG, 0x00000002); - etna_set_state(stream, VIVS_VS_ICACHE_CONTROL, VIVS_VS_ICACHE_CONTROL_ENABLE); + etna_set_state(stream, VIVS_SH_ICACHE_CONTROL, VIVS_SH_ICACHE_CONTROL_ENABLE); etna_set_state(stream, VIVS_PS_ICACHE_COUNT, ctx->shader_state.ps_inst_mem_size / 4 - 1); } else if (ctx->shader_state.VS_INST_ADDR.bo || ctx->shader_state.PS_INST_ADDR.bo) { @@ -674,18 +674,18 @@ etna_emit_state(struct etna_context *ctx) /* Set icache (VS) */ etna_set_state(stream, VIVS_VS_RANGE, VIVS_VS_RANGE_HIGH(ctx->shader_state.vs_inst_mem_size / 4 - 1)); - etna_set_state(stream, VIVS_VS_ICACHE_CONTROL, - VIVS_VS_ICACHE_CONTROL_ENABLE | - VIVS_VS_ICACHE_CONTROL_FLUSH_VS); + etna_set_state(stream, VIVS_SH_ICACHE_CONTROL, + VIVS_SH_ICACHE_CONTROL_ENABLE | + VIVS_SH_ICACHE_CONTROL_FLUSH_VS); assert(ctx->shader_state.VS_INST_ADDR.bo); etna_set_state_reloc(stream, VIVS_VS_INST_ADDR, &ctx->shader_state.VS_INST_ADDR); /* Set icache (PS) */ etna_set_state(stream, VIVS_PS_RANGE, VIVS_PS_RANGE_HIGH(ctx->shader_state.ps_inst_mem_size / 4 - 1)); - etna_set_state(stream, VIVS_VS_ICACHE_CONTROL, - VIVS_VS_ICACHE_CONTROL_ENABLE | - VIVS_VS_ICACHE_CONTROL_FLUSH_PS); + etna_set_state(stream, VIVS_SH_ICACHE_CONTROL, + VIVS_SH_ICACHE_CONTROL_ENABLE | + VIVS_SH_ICACHE_CONTROL_FLUSH_PS); assert(ctx->shader_state.PS_INST_ADDR.bo); etna_set_state_reloc(stream, VIVS_PS_INST_ADDR, &ctx->shader_state.PS_INST_ADDR); } else { @@ -694,9 +694,9 @@ etna_emit_state(struct etna_context *ctx) /* Upload shader directly, first flushing and disabling icache if * supported on this hw */ if (screen->specs.has_icache) { - etna_set_state(stream, VIVS_VS_ICACHE_CONTROL, - VIVS_VS_ICACHE_CONTROL_FLUSH_PS | - VIVS_VS_ICACHE_CONTROL_FLUSH_VS); + etna_set_state(stream, VIVS_SH_ICACHE_CONTROL, + VIVS_SH_ICACHE_CONTROL_FLUSH_PS | + VIVS_SH_ICACHE_CONTROL_FLUSH_VS); } if (screen->specs.has_unified_instmem) { etna_set_state(stream, VIVS_VS_RANGE, @@ -723,12 +723,12 @@ etna_emit_state(struct etna_context *ctx) } if (do_uniform_flush) - etna_set_state(stream, VIVS_VS_UNIFORM_CACHE, VIVS_VS_UNIFORM_CACHE_FLUSH); + etna_set_state(stream, VIVS_SH_CONTROL, VIVS_SH_CONTROL_PS_CODE); etna_uniforms_write(ctx, ctx->shader.vs, ctx->constant_buffer[PIPE_SHADER_VERTEX].cb); if (do_uniform_flush) - etna_set_state(stream, VIVS_VS_UNIFORM_CACHE, VIVS_VS_UNIFORM_CACHE_FLUSH | VIVS_VS_UNIFORM_CACHE_PS); + etna_set_state(stream, VIVS_SH_CONTROL, VIVS_SH_CONTROL_PS_CODE | VIVS_SH_CONTROL_PS_UNIFORM); etna_uniforms_write(ctx, ctx->shader.fs, ctx->constant_buffer[PIPE_SHADER_FRAGMENT].cb); @@ -741,14 +741,14 @@ etna_emit_state(struct etna_context *ctx) } else { /* ideally this cache would only be flushed if there are VS uniform changes */ if (do_uniform_flush) - etna_set_state(stream, VIVS_VS_UNIFORM_CACHE, VIVS_VS_UNIFORM_CACHE_FLUSH); + etna_set_state(stream, VIVS_SH_CONTROL, VIVS_SH_CONTROL_PS_CODE); if (dirty & (uniform_dirty_bits | ctx->shader.vs->uniforms_dirty_bits)) etna_uniforms_write(ctx, ctx->shader.vs, ctx->constant_buffer[PIPE_SHADER_VERTEX].cb); /* ideally this cache would only be flushed if there are PS uniform changes */ if (do_uniform_flush) - etna_set_state(stream, VIVS_VS_UNIFORM_CACHE, VIVS_VS_UNIFORM_CACHE_FLUSH | VIVS_VS_UNIFORM_CACHE_PS); + etna_set_state(stream, VIVS_SH_CONTROL, VIVS_SH_CONTROL_PS_CODE | VIVS_SH_CONTROL_PS_UNIFORM); if (dirty & (uniform_dirty_bits | ctx->shader.fs->uniforms_dirty_bits)) etna_uniforms_write(ctx, ctx->shader.fs, ctx->constant_buffer[PIPE_SHADER_FRAGMENT].cb);