From afea98593ebd994820de9691194e73267ec3385b Mon Sep 17 00:00:00 2001 From: Lionel Landwerlin Date: Tue, 22 Apr 2025 18:27:47 +0300 Subject: [PATCH] nir: add a new intrinsic for load dynamic tessellation config Signed-off-by: Lionel Landwerlin Reviewed-by: Caio Oliveira Reviewed-by: Alyssa Rosenzweig Part-of: --- src/compiler/nir/nir_divergence_analysis.c | 1 + src/compiler/nir/nir_intrinsics.py | 5 ++++- 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/src/compiler/nir/nir_divergence_analysis.c b/src/compiler/nir/nir_divergence_analysis.c index fb691bcff5f..00c9047c411 100644 --- a/src/compiler/nir/nir_divergence_analysis.c +++ b/src/compiler/nir/nir_divergence_analysis.c @@ -362,6 +362,7 @@ visit_intrinsic(nir_intrinsic_instr *instr, struct divergence_state *state) case nir_intrinsic_load_core_count_arm: case nir_intrinsic_load_core_max_id_arm: case nir_intrinsic_load_warp_max_id_arm: + case nir_intrinsic_load_tess_config_intel: is_divergent = false; break; diff --git a/src/compiler/nir/nir_intrinsics.py b/src/compiler/nir/nir_intrinsics.py index ed38714f4bb..f84413acafb 100644 --- a/src/compiler/nir/nir_intrinsics.py +++ b/src/compiler/nir/nir_intrinsics.py @@ -2474,7 +2474,10 @@ intrinsic("load_inline_data_intel", [], dest_comp=0, indices=[BASE], flags=[CAN_ELIMINATE, CAN_REORDER]) -# Dynamic fragment shader parameters. +# Dynamic tesselation parameters (see intel_tess_config). +system_value("tess_config_intel", 1) + +# Dynamic fragment shader parameters (see intel_msaa_flags) . system_value("fs_msaa_intel", 1) # Per primitive remapping table offset.