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intel: Limit the D16 workarounds to Gfx12.0

Browse source 
The workarounds introduced in cd40110420 are no longer needed on
Gfx12.5.

Suggested-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10939>
This commit is contained in:
Nanley Chery 2021-05-21 14:50:38 -07:00 • committed by Marge Bot
parent 07b86e64a5
commit afe3f373a4
4 changed files with 4 additions and 4 deletions
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2
src/gallium/drivers/iris/iris_state.c
View file

@ -6231,7 +6231,7 @@ iris_upload_dirty_render_state(struct iris_context *ice,
uint32_t clear_length = GENX(3DSTATE_CLEAR_PARAMS_length) * 4;
uint32_t cso_z_size = batch->screen->isl_dev.ds.size - clear_length;;
#if GFX_VER == 12
#if GFX_VERx10 == 120
/* Wa_14010455700
*
* ISL will change some CHICKEN registers depending on the depth surface

2
src/intel/isl/isl.c
View file

@ -266,7 +266,7 @@ isl_device_init(struct isl_device *dev,
dev->ds.hiz_offset = 0;
}
if (ISL_GFX_VER(dev) >= 12) {
if (ISL_GFX_VERX10(dev) == 120) {
dev->ds.size += GFX12_MI_LOAD_REGISTER_IMM_length * 4 * 2;
}

2
src/intel/isl/isl_emit_depth_stencil.c
View file

@ -304,7 +304,7 @@ isl_genX(emit_depth_stencil_hiz_s)(const struct isl_device *dev, void *batch,
GENX(3DSTATE_HIER_DEPTH_BUFFER_pack)(NULL, dw, &hiz);
dw += GENX(3DSTATE_HIER_DEPTH_BUFFER_length);
#if GFX_VER == 12
#if GFX_VERx10 == 120
/* Wa_14010455700
*
* To avoid sporadic corruptions “Set 0x7010[9] when Depth Buffer Surface

2
src/intel/vulkan/genX_cmd_buffer.c
View file

@ -5705,7 +5705,7 @@ cmd_buffer_begin_subpass(struct anv_cmd_buffer *cmd_buffer,
ANV_PIPE_STALL_AT_SCOREBOARD_BIT;
#endif
#if GFX_VER == 12
#if GFX_VERx10 == 120
/* Wa_14010455700
*
* ISL will change some CHICKEN registers depending on the depth surface