From afe3f373a434aebd0ed2bbd7654da34a5b8ad24e Mon Sep 17 00:00:00 2001 From: Nanley Chery Date: Fri, 21 May 2021 14:50:38 -0700 Subject: [PATCH] intel: Limit the D16 workarounds to Gfx12.0 The workarounds introduced in cd40110420b are no longer needed on Gfx12.5. Suggested-by: Lionel Landwerlin Reviewed-by: Lionel Landwerlin Part-of: --- src/gallium/drivers/iris/iris_state.c | 2 +- src/intel/isl/isl.c | 2 +- src/intel/isl/isl_emit_depth_stencil.c | 2 +- src/intel/vulkan/genX_cmd_buffer.c | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) diff --git a/src/gallium/drivers/iris/iris_state.c b/src/gallium/drivers/iris/iris_state.c index b3a6c19a070..1f579308565 100644 --- a/src/gallium/drivers/iris/iris_state.c +++ b/src/gallium/drivers/iris/iris_state.c @@ -6231,7 +6231,7 @@ iris_upload_dirty_render_state(struct iris_context *ice, uint32_t clear_length = GENX(3DSTATE_CLEAR_PARAMS_length) * 4; uint32_t cso_z_size = batch->screen->isl_dev.ds.size - clear_length;; -#if GFX_VER == 12 +#if GFX_VERx10 == 120 /* Wa_14010455700 * * ISL will change some CHICKEN registers depending on the depth surface diff --git a/src/intel/isl/isl.c b/src/intel/isl/isl.c index 232bd95e065..173c3563562 100644 --- a/src/intel/isl/isl.c +++ b/src/intel/isl/isl.c @@ -266,7 +266,7 @@ isl_device_init(struct isl_device *dev, dev->ds.hiz_offset = 0; } - if (ISL_GFX_VER(dev) >= 12) { + if (ISL_GFX_VERX10(dev) == 120) { dev->ds.size += GFX12_MI_LOAD_REGISTER_IMM_length * 4 * 2; } diff --git a/src/intel/isl/isl_emit_depth_stencil.c b/src/intel/isl/isl_emit_depth_stencil.c index bfd290e5ad9..c337205bc71 100644 --- a/src/intel/isl/isl_emit_depth_stencil.c +++ b/src/intel/isl/isl_emit_depth_stencil.c @@ -304,7 +304,7 @@ isl_genX(emit_depth_stencil_hiz_s)(const struct isl_device *dev, void *batch, GENX(3DSTATE_HIER_DEPTH_BUFFER_pack)(NULL, dw, &hiz); dw += GENX(3DSTATE_HIER_DEPTH_BUFFER_length); -#if GFX_VER == 12 +#if GFX_VERx10 == 120 /* Wa_14010455700 * * To avoid sporadic corruptions “Set 0x7010[9] when Depth Buffer Surface diff --git a/src/intel/vulkan/genX_cmd_buffer.c b/src/intel/vulkan/genX_cmd_buffer.c index 54b76406cfe..0ede40214e7 100644 --- a/src/intel/vulkan/genX_cmd_buffer.c +++ b/src/intel/vulkan/genX_cmd_buffer.c @@ -5705,7 +5705,7 @@ cmd_buffer_begin_subpass(struct anv_cmd_buffer *cmd_buffer, ANV_PIPE_STALL_AT_SCOREBOARD_BIT; #endif -#if GFX_VER == 12 +#if GFX_VERx10 == 120 /* Wa_14010455700 * * ISL will change some CHICKEN registers depending on the depth surface