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aco/isel: rename emit_readfirstlane() -> emit_vector_as_uniform()

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Also allow to use p_as_uniform and improve vector splitting.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36133>
(cherry picked from commit 4632ee4c37)
This commit is contained in:
Daniel Schürmann 2025-07-14 21:59:29 +02:00 • committed by Eric Engestrom
parent 0dcca970a5
commit af7843a219
2 changed files with 21 additions and 18 deletions
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2
.pick_status.json
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@ -25154,7 +25154,7 @@
"description": "aco/isel: rename emit_readfirstlane() -> emit_vector_as_uniform()",
"nominated": false,
"nomination_type": 0,
"resolution": 4,
"resolution": 1,
"main_sha": null,
"because_sha": null,
"notes": null

37
src/amd/compiler/instruction_selection/aco_select_nir_intrinsics.cpp
View file

@ -181,14 +181,18 @@ emit_extract_vector(isel_context* ctx, Temp src, uint32_t idx, Temp dst)
}
Temp
emit_readfirstlane(isel_context* ctx, Temp src, Temp dst)
emit_vector_as_uniform(isel_context* ctx, Temp src, Temp dst,
bool readfirstlane_for_uniform = false)
{
Builder bld(ctx->program, ctx->block);
if (src.regClass().type() == RegType::sgpr) {
bld.copy(Definition(dst), src);
} else if (src.size() == 1) {
bld.vop1(aco_opcode::v_readfirstlane_b32, Definition(dst), src);
if (readfirstlane_for_uniform)
bld.vop1(aco_opcode::v_readfirstlane_b32, Definition(dst), src);
else
bld.pseudo(aco_opcode::p_as_uniform, Definition(dst), src);
} else {
aco_ptr<Instruction> split{
create_instruction(aco_opcode::p_split_vector, Format::PSEUDO, 1, src.size())};
@ -202,17 +206,22 @@ emit_readfirstlane(isel_context* ctx, Temp src, Temp dst)
Instruction* split_raw = split.get();
ctx->block->instructions.emplace_back(std::move(split));
std::array<Temp, NIR_MAX_VEC_COMPONENTS> elems;
aco_ptr<Instruction> vec{
create_instruction(aco_opcode::p_create_vector, Format::PSEUDO, src.size(), 1)};
vec->definitions[0] = Definition(dst);
for (unsigned i = 0; i < src.size(); i++) {
vec->operands[i] = bld.vop1(aco_opcode::v_readfirstlane_b32, bld.def(s1),
split_raw->definitions[i].getTemp());
if (readfirstlane_for_uniform)
vec->operands[i] = bld.vop1(aco_opcode::v_readfirstlane_b32, bld.def(s1),
split_raw->definitions[i].getTemp());
else
vec->operands[i] = bld.pseudo(aco_opcode::p_as_uniform, bld.def(s1),
split_raw->definitions[i].getTemp());
elems[i] = vec->operands[i].getTemp();
}
ctx->block->instructions.emplace_back(std::move(vec));
if (src.bytes() % 4 == 0)
emit_split_vector(ctx, dst, src.size());
ctx->allocated_vec.emplace(dst.id(), elems);
}
return dst;
@ -431,12 +440,9 @@ emit_load(isel_context* ctx, Builder& bld, const LoadEmitInfo& info,
* also update allocated_vec */
for (unsigned j = start; j < components_split; j++) {
if (allocated_vec[j].bytes() % 4 == 0 && info.dst.type() == RegType::sgpr) {
if (info.readfirstlane_for_uniform) {
allocated_vec[j] = emit_readfirstlane(
ctx, allocated_vec[j], bld.tmp(RegClass(RegType::sgpr, allocated_vec[j].size())));
} else {
allocated_vec[j] = bld.as_uniform(allocated_vec[j]);
}
allocated_vec[j] = emit_vector_as_uniform(
ctx, allocated_vec[j], bld.tmp(RegClass(RegType::sgpr, allocated_vec[j].size())),
info.readfirstlane_for_uniform);
}
has_vgprs |= allocated_vec[j].type() == RegType::vgpr;
}
@ -459,10 +465,7 @@ emit_load(isel_context* ctx, Builder& bld, const LoadEmitInfo& info,
Temp tmp = bld.tmp(RegType::vgpr, info.dst.size());
vec->definitions[0] = Definition(tmp);
bld.insert(std::move(vec));
if (info.readfirstlane_for_uniform)
emit_readfirstlane(ctx, tmp, info.dst);
else
bld.pseudo(aco_opcode::p_as_uniform, Definition(info.dst), tmp);
emit_vector_as_uniform(ctx, tmp, info.dst, info.readfirstlane_for_uniform);
} else {
vec->definitions[0] = Definition(info.dst);
bld.insert(std::move(vec));
@ -4438,7 +4441,7 @@ visit_intrinsic(isel_context* ctx, nir_intrinsic_instr* instr)
bld.sop1(Builder::s_ff1_i32, bld.def(s1), Operand(exec, bld.lm)));
bool_to_vector_condition(ctx, tmp, dst);
} else {
emit_readfirstlane(ctx, src, dst);
emit_vector_as_uniform(ctx, src, dst, true);
}
set_wqm(ctx);
break;