From af7843a21944f6ac90e0786728df98b47a393b5c Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Daniel=20Sch=C3=BCrmann?= Date: Mon, 14 Jul 2025 21:59:29 +0200 Subject: [PATCH] aco/isel: rename emit_readfirstlane() -> emit_vector_as_uniform() Also allow to use p_as_uniform and improve vector splitting. Part-of: (cherry picked from commit 4632ee4c376808842dc717549b090818762e743d) --- .pick_status.json | 2 +- .../aco_select_nir_intrinsics.cpp | 37 ++++++++++--------- 2 files changed, 21 insertions(+), 18 deletions(-) diff --git a/.pick_status.json b/.pick_status.json index 6f93c61f088..8e5b46fc359 100644 --- a/.pick_status.json +++ b/.pick_status.json @@ -25154,7 +25154,7 @@ "description": "aco/isel: rename emit_readfirstlane() -> emit_vector_as_uniform()", "nominated": false, "nomination_type": 0, - "resolution": 4, + "resolution": 1, "main_sha": null, "because_sha": null, "notes": null diff --git a/src/amd/compiler/instruction_selection/aco_select_nir_intrinsics.cpp b/src/amd/compiler/instruction_selection/aco_select_nir_intrinsics.cpp index 733fe11fa34..6a218716c5b 100644 --- a/src/amd/compiler/instruction_selection/aco_select_nir_intrinsics.cpp +++ b/src/amd/compiler/instruction_selection/aco_select_nir_intrinsics.cpp @@ -181,14 +181,18 @@ emit_extract_vector(isel_context* ctx, Temp src, uint32_t idx, Temp dst) } Temp -emit_readfirstlane(isel_context* ctx, Temp src, Temp dst) +emit_vector_as_uniform(isel_context* ctx, Temp src, Temp dst, + bool readfirstlane_for_uniform = false) { Builder bld(ctx->program, ctx->block); if (src.regClass().type() == RegType::sgpr) { bld.copy(Definition(dst), src); } else if (src.size() == 1) { - bld.vop1(aco_opcode::v_readfirstlane_b32, Definition(dst), src); + if (readfirstlane_for_uniform) + bld.vop1(aco_opcode::v_readfirstlane_b32, Definition(dst), src); + else + bld.pseudo(aco_opcode::p_as_uniform, Definition(dst), src); } else { aco_ptr split{ create_instruction(aco_opcode::p_split_vector, Format::PSEUDO, 1, src.size())}; @@ -202,17 +206,22 @@ emit_readfirstlane(isel_context* ctx, Temp src, Temp dst) Instruction* split_raw = split.get(); ctx->block->instructions.emplace_back(std::move(split)); + std::array elems; aco_ptr vec{ create_instruction(aco_opcode::p_create_vector, Format::PSEUDO, src.size(), 1)}; vec->definitions[0] = Definition(dst); for (unsigned i = 0; i < src.size(); i++) { - vec->operands[i] = bld.vop1(aco_opcode::v_readfirstlane_b32, bld.def(s1), - split_raw->definitions[i].getTemp()); + if (readfirstlane_for_uniform) + vec->operands[i] = bld.vop1(aco_opcode::v_readfirstlane_b32, bld.def(s1), + split_raw->definitions[i].getTemp()); + else + vec->operands[i] = bld.pseudo(aco_opcode::p_as_uniform, bld.def(s1), + split_raw->definitions[i].getTemp()); + elems[i] = vec->operands[i].getTemp(); } ctx->block->instructions.emplace_back(std::move(vec)); - if (src.bytes() % 4 == 0) - emit_split_vector(ctx, dst, src.size()); + ctx->allocated_vec.emplace(dst.id(), elems); } return dst; @@ -431,12 +440,9 @@ emit_load(isel_context* ctx, Builder& bld, const LoadEmitInfo& info, * also update allocated_vec */ for (unsigned j = start; j < components_split; j++) { if (allocated_vec[j].bytes() % 4 == 0 && info.dst.type() == RegType::sgpr) { - if (info.readfirstlane_for_uniform) { - allocated_vec[j] = emit_readfirstlane( - ctx, allocated_vec[j], bld.tmp(RegClass(RegType::sgpr, allocated_vec[j].size()))); - } else { - allocated_vec[j] = bld.as_uniform(allocated_vec[j]); - } + allocated_vec[j] = emit_vector_as_uniform( + ctx, allocated_vec[j], bld.tmp(RegClass(RegType::sgpr, allocated_vec[j].size())), + info.readfirstlane_for_uniform); } has_vgprs |= allocated_vec[j].type() == RegType::vgpr; } @@ -459,10 +465,7 @@ emit_load(isel_context* ctx, Builder& bld, const LoadEmitInfo& info, Temp tmp = bld.tmp(RegType::vgpr, info.dst.size()); vec->definitions[0] = Definition(tmp); bld.insert(std::move(vec)); - if (info.readfirstlane_for_uniform) - emit_readfirstlane(ctx, tmp, info.dst); - else - bld.pseudo(aco_opcode::p_as_uniform, Definition(info.dst), tmp); + emit_vector_as_uniform(ctx, tmp, info.dst, info.readfirstlane_for_uniform); } else { vec->definitions[0] = Definition(info.dst); bld.insert(std::move(vec)); @@ -4438,7 +4441,7 @@ visit_intrinsic(isel_context* ctx, nir_intrinsic_instr* instr) bld.sop1(Builder::s_ff1_i32, bld.def(s1), Operand(exec, bld.lm))); bool_to_vector_condition(ctx, tmp, dst); } else { - emit_readfirstlane(ctx, src, dst); + emit_vector_as_uniform(ctx, src, dst, true); } set_wqm(ctx); break;