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tu: Allow reg stomping of compute related registers

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We don't use draw states for dispatches, so the bound pipeline
could be overwritten by reg stomping in a renderpass or blit.

The solution is to re-emit pipeline's IB on every dispatch if
reg stomping is used.

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23881>
This commit is contained in:
Danylo Piliaiev 2023-07-11 14:33:10 +02:00 • committed by Marge Bot
parent dac8d371e1
commit aecb732320
1 changed files with 7 additions and 0 deletions
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7
src/freedreno/vulkan/tu_cmd_buffer.cc
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@ -5120,6 +5120,13 @@ tu_dispatch(struct tu_cmd_buffer *cmd,
pipeline->instrlen >
cmd->device->physical_device->info->a6xx.instr_cache_size;
/* We don't use draw states for dispatches, so the bound pipeline
* could be overwritten by reg stomping in a renderpass or blit.
*/
if (cmd->device->dbg_renderpass_stomp_cs) {
tu_cs_emit_state_ib(&cmd->cs, cmd->state.compute_pipeline->base.program.state);
}
/* There appears to be a HW bug where in some rare circumstances it appears
* to accidentally use the FS instrlen instead of the CS instrlen, which
* affects all known gens. Based on various experiments it appears that the