From aecb73232079ff03cdbe85d389aa99f07b172a90 Mon Sep 17 00:00:00 2001 From: Danylo Piliaiev Date: Tue, 11 Jul 2023 14:33:10 +0200 Subject: [PATCH] tu: Allow reg stomping of compute related registers We don't use draw states for dispatches, so the bound pipeline could be overwritten by reg stomping in a renderpass or blit. The solution is to re-emit pipeline's IB on every dispatch if reg stomping is used. Signed-off-by: Danylo Piliaiev Part-of: --- src/freedreno/vulkan/tu_cmd_buffer.cc | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/src/freedreno/vulkan/tu_cmd_buffer.cc b/src/freedreno/vulkan/tu_cmd_buffer.cc index 5905821bc2c..015ee38bbe0 100644 --- a/src/freedreno/vulkan/tu_cmd_buffer.cc +++ b/src/freedreno/vulkan/tu_cmd_buffer.cc @@ -5120,6 +5120,13 @@ tu_dispatch(struct tu_cmd_buffer *cmd, pipeline->instrlen > cmd->device->physical_device->info->a6xx.instr_cache_size; + /* We don't use draw states for dispatches, so the bound pipeline + * could be overwritten by reg stomping in a renderpass or blit. + */ + if (cmd->device->dbg_renderpass_stomp_cs) { + tu_cs_emit_state_ib(&cmd->cs, cmd->state.compute_pipeline->base.program.state); + } + /* There appears to be a HW bug where in some rare circumstances it appears * to accidentally use the FS instrlen instead of the CS instrlen, which * affects all known gens. Based on various experiments it appears that the