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intel/blorp: Program DispatchWalkOrder and ThreadGroupBatchSize with optimized values for regular computer walkers

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It was only added to indirect compute walkers while HSD don't say
anything about this optimization be specific to indirect compute
walkers.

Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36058>
This commit is contained in:
José Roberto de Souza 2025-07-10 11:53:05 -07:00 • committed by Marge Bot
parent 06997a42a3
commit aea519cbc2
1 changed files with 5 additions and 0 deletions
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5
src/intel/blorp/blorp_genX_exec_brw.h
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@ -1785,6 +1785,11 @@ blorp_exec_compute(struct blorp_batch *batch, const struct blorp_params *params)
.TileLayout = cs_prog_data->walk_order == INTEL_WALK_ORDER_YXZ ?
TileY32bpe : Linear,
#endif
#if GFX_VER >= 30
/* HSD 14016252163 */
.DispatchWalkOrder = cs_prog_data->uses_sampler ? MortonWalk : LinearWalk,
.ThreadGroupBatchSize = cs_prog_data->uses_sampler ? TG_BATCH_4 : TG_BATCH_1,
#endif
.InterfaceDescriptor = (struct GENX(INTERFACE_DESCRIPTOR_DATA)) {
.KernelStartPointer = params->cs_prog_kernel,