From aea519cbc247a3335b88e2906bbd0e9bdc210d4e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Roberto=20de=20Souza?= Date: Thu, 10 Jul 2025 11:53:05 -0700 Subject: [PATCH] intel/blorp: Program DispatchWalkOrder and ThreadGroupBatchSize with optimized values for regular computer walkers MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit It was only added to indirect compute walkers while HSD don't say anything about this optimization be specific to indirect compute walkers. Reviewed-by: Sagar Ghuge Signed-off-by: José Roberto de Souza Part-of: --- src/intel/blorp/blorp_genX_exec_brw.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/src/intel/blorp/blorp_genX_exec_brw.h b/src/intel/blorp/blorp_genX_exec_brw.h index c923c82b599..afbd470c9f8 100644 --- a/src/intel/blorp/blorp_genX_exec_brw.h +++ b/src/intel/blorp/blorp_genX_exec_brw.h @@ -1785,6 +1785,11 @@ blorp_exec_compute(struct blorp_batch *batch, const struct blorp_params *params) .TileLayout = cs_prog_data->walk_order == INTEL_WALK_ORDER_YXZ ? TileY32bpe : Linear, #endif +#if GFX_VER >= 30 + /* HSD 14016252163 */ + .DispatchWalkOrder = cs_prog_data->uses_sampler ? MortonWalk : LinearWalk, + .ThreadGroupBatchSize = cs_prog_data->uses_sampler ? TG_BATCH_4 : TG_BATCH_1, +#endif .InterfaceDescriptor = (struct GENX(INTERFACE_DESCRIPTOR_DATA)) { .KernelStartPointer = params->cs_prog_kernel,