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ac/gpu_info: disable display DCC on Raphael and Mendocino to improve power usage

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Below is the summary from the power validation.. "it looks like the only
workload where I see savings from DCC is PLT and it is only about 65mW
which is just run to run variation. For Idle I am seeing ~280mW increase
in power, ~200mW increase for power_VideoCall, and ~80mW increase for VP"

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22771>
This commit is contained in:
Marek Olšák 2023-04-29 04:58:41 -04:00 • committed by Marge Bot
parent e4c8ac5aae
commit ae6b928495
1 changed files with 8 additions and 3 deletions
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11
src/amd/common/ac_gpu_info.c
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@ -1277,10 +1277,15 @@ bool ac_query_gpu_info(int fd, void *dev_p, struct radeon_info *info)
info->family == CHIP_RENOIR)) ||
info->gfx_level >= GFX10_3) {
/* GFX10+ requires retiling in all cases. */
if (info->max_render_backends == 1 && info->gfx_level == GFX9)
if (info->max_render_backends == 1 && info->gfx_level == GFX9) {
info->use_display_dcc_unaligned = true;
else
info->use_display_dcc_with_retile_blit = true;
} else {
/* Displayable DCC with retiling is known to increase power consumption on Raphael
* and Mendocino, so disable it on the smallest APUs. We need a proof that
* displayable DCC doesn't regress bigger chips in the same way.
*/
info->use_display_dcc_with_retile_blit = info->num_cu > 4;
}
}
info->has_stable_pstate = info->drm_minor >= 45;