From ae6b9284951064f81a7e9343fbfa731f643121a1 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Marek=20Ol=C5=A1=C3=A1k?= Date: Sat, 29 Apr 2023 04:58:41 -0400 Subject: [PATCH] ac/gpu_info: disable display DCC on Raphael and Mendocino to improve power usage Below is the summary from the power validation.. "it looks like the only workload where I see savings from DCC is PLT and it is only about 65mW which is just run to run variation. For Idle I am seeing ~280mW increase in power, ~200mW increase for power_VideoCall, and ~80mW increase for VP" Reviewed-by: Pierre-Eric Pelloux-Prayer Part-of: --- src/amd/common/ac_gpu_info.c | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/src/amd/common/ac_gpu_info.c b/src/amd/common/ac_gpu_info.c index aca5454101c..cb17ba11701 100644 --- a/src/amd/common/ac_gpu_info.c +++ b/src/amd/common/ac_gpu_info.c @@ -1277,10 +1277,15 @@ bool ac_query_gpu_info(int fd, void *dev_p, struct radeon_info *info) info->family == CHIP_RENOIR)) || info->gfx_level >= GFX10_3) { /* GFX10+ requires retiling in all cases. */ - if (info->max_render_backends == 1 && info->gfx_level == GFX9) + if (info->max_render_backends == 1 && info->gfx_level == GFX9) { info->use_display_dcc_unaligned = true; - else - info->use_display_dcc_with_retile_blit = true; + } else { + /* Displayable DCC with retiling is known to increase power consumption on Raphael + * and Mendocino, so disable it on the smallest APUs. We need a proof that + * displayable DCC doesn't regress bigger chips in the same way. + */ + info->use_display_dcc_with_retile_blit = info->num_cu > 4; + } } info->has_stable_pstate = info->drm_minor >= 45;