From ad83c06a5f880a1d836e17ef76e7382eb9b6222b Mon Sep 17 00:00:00 2001 From: Samuel Pitoiset Date: Mon, 2 Aug 2021 16:43:15 +0200 Subject: [PATCH] radv: fix missing cache flushes when clearing HTILE levels on GFX10+ The driver should accumulate the cache flush bits because if it uses CP DMA for clearing the last level, it won't flush. Found by inspection. Cc: 21.2 mesa-stable Signed-off-by: Samuel Pitoiset Reviewed-by: Bas Nieuwenhuizen Part-of: --- src/amd/vulkan/radv_meta_clear.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/amd/vulkan/radv_meta_clear.c b/src/amd/vulkan/radv_meta_clear.c index 3ad4040fe1c..65543c0fdf9 100644 --- a/src/amd/vulkan/radv_meta_clear.c +++ b/src/amd/vulkan/radv_meta_clear.c @@ -1389,10 +1389,10 @@ radv_clear_htile(struct radv_cmd_buffer *cmd_buffer, const struct radv_image *im if (htile_mask == UINT_MAX) { /* Clear the whole HTILE buffer. */ - flush_bits = radv_fill_buffer(cmd_buffer, image, image->bo, offset, size, value); + flush_bits |= radv_fill_buffer(cmd_buffer, image, image->bo, offset, size, value); } else { /* Only clear depth or stencil bytes in the HTILE buffer. */ - flush_bits = + flush_bits |= clear_htile_mask(cmd_buffer, image, image->bo, offset, size, value, htile_mask); } }