fdo-mirrors/mesa
1
0
Fork 0
mirror of https://gitlab.freedesktop.org/mesa/mesa.git synced 2026-05-08 11:18:08 +02:00
Code Issues Projects Releases Packages Wiki Activity Actions 1

iris: implement state cache invalidate for Wa_16013063087

Browse source 
Cc: mesa-stable
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22651>
(cherry picked from commit 5e5ca30785)
This commit is contained in:
Tapani Pälli 2023-04-24 08:52:28 +03:00 • committed by Eric Engestrom
parent a1016ce65c
commit 49d09360b5
2 changed files with 11 additions and 1 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

2
.pick_status.json
View file

@ -796,7 +796,7 @@
"description": "iris: implement state cache invalidate for Wa_16013063087",
"nominated": true,
"nomination_type": 0,
"resolution": 0,
"resolution": 1,
"main_sha": null,
"because_sha": null
},

10
src/gallium/drivers/iris/iris_state.c
View file

@ -660,6 +660,16 @@ emit_pipeline_select(struct iris_batch *batch, uint32_t pipeline)
} else {
flags |= PIPE_CONTROL_UNTYPED_DATAPORT_CACHE_FLUSH;
}
/* Wa_16013063087 - State Cache Invalidate must be issued prior to
* PIPELINE_SELECT when switching from 3D to Compute.
*
* SW must do this by programming of PIPECONTROL with “CS Stall” followed
* by a PIPECONTROL with State Cache Invalidate bit set.
*/
if (pipeline == GPGPU &&
intel_needs_workaround(batch->screen->devinfo, 16013063087))
flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
iris_emit_pipe_control_flush(batch, "PIPELINE_SELECT flush", flags);
#else
/* From "BXML » GT » MI » vol1a GPU Overview » [Instruction]