From a8d2ef8bd6e34eef4dbab1a078ea27d35538d554 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Marek=20Ol=C5=A1=C3=A1k?= Date: Sat, 14 May 2022 02:19:56 -0400 Subject: [PATCH] radeonsi/gfx11: don't insert shader code for GS_PIPELINE_STATS_EMU GS_PIPELINE_STATS_EMU is always false, so the branches were never entered. Reviewed-by: Mihai Preda Reviewed-by: Pierre-Eric Pelloux-Prayer Part-of: --- .../drivers/radeonsi/gfx10_shader_ngg.c | 80 ++++++++++--------- 1 file changed, 42 insertions(+), 38 deletions(-) diff --git a/src/gallium/drivers/radeonsi/gfx10_shader_ngg.c b/src/gallium/drivers/radeonsi/gfx10_shader_ngg.c index 05034684ee0..0185a8194ac 100644 --- a/src/gallium/drivers/radeonsi/gfx10_shader_ngg.c +++ b/src/gallium/drivers/radeonsi/gfx10_shader_ngg.c @@ -1853,27 +1853,29 @@ void gfx10_ngg_gs_emit_begin(struct si_shader_context *ctx) } ac_build_endif(&ctx->ac, 5090); - tmp = si_is_gs_thread(ctx); - ac_build_ifcc(&ctx->ac, tmp, 15090); - { - tmp = si_unpack_param(ctx, ctx->vs_state_bits, 31, 1); - tmp = LLVMBuildTrunc(builder, tmp, ctx->ac.i1, ""); - ac_build_ifcc(&ctx->ac, tmp, 5109); /* if (GS_PIPELINE_STATS_EMU) */ - LLVMValueRef args[] = { - ctx->ac.i32_1, - ngg_get_emulated_counters_buf(ctx), - LLVMConstInt(ctx->ac.i32, - (si_hw_query_dw_offset(PIPE_STAT_QUERY_GS_INVOCATIONS) + - SI_QUERY_STATS_END_OFFSET_DW) * 4, - false), - ctx->ac.i32_0, /* soffset */ - ctx->ac.i32_0, /* cachepolicy */ - }; + if (ctx->screen->info.gfx_level < GFX11) { + tmp = si_is_gs_thread(ctx); + ac_build_ifcc(&ctx->ac, tmp, 15090); + { + tmp = si_unpack_param(ctx, ctx->vs_state_bits, 31, 1); + tmp = LLVMBuildTrunc(builder, tmp, ctx->ac.i1, ""); + ac_build_ifcc(&ctx->ac, tmp, 5109); /* if (GS_PIPELINE_STATS_EMU) */ + LLVMValueRef args[] = { + ctx->ac.i32_1, + ngg_get_emulated_counters_buf(ctx), + LLVMConstInt(ctx->ac.i32, + (si_hw_query_dw_offset(PIPE_STAT_QUERY_GS_INVOCATIONS) + + SI_QUERY_STATS_END_OFFSET_DW) * 4, + false), + ctx->ac.i32_0, /* soffset */ + ctx->ac.i32_0, /* cachepolicy */ + }; - ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.raw.buffer.atomic.add.i32", ctx->ac.i32, args, 5, 0); - ac_build_endif(&ctx->ac, 5109); - } - ac_build_endif(&ctx->ac, 15090); + ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.raw.buffer.atomic.add.i32", ctx->ac.i32, args, 5, 0); + ac_build_endif(&ctx->ac, 5109); + } + ac_build_endif(&ctx->ac, 15090); + } ac_build_waitcnt(&ctx->ac, AC_WAIT_LGKM); ac_build_s_barrier(&ctx->ac, ctx->stage); @@ -2183,26 +2185,28 @@ void gfx10_ngg_gs_build_end(struct si_shader_context *ctx) ac_build_export_prim(&ctx->ac, &prim); - tmp = si_unpack_param(ctx, ctx->vs_state_bits, 31, 1); - tmp = LLVMBuildTrunc(builder, tmp, ctx->ac.i1, ""); - ac_build_ifcc(&ctx->ac, tmp, 5229); /* if (GS_PIPELINE_STATS_EMU) */ - ac_build_ifcc(&ctx->ac, LLVMBuildNot(builder, prim.isnull, ""), 5237); - { - LLVMValueRef args[] = { - ctx->ac.i32_1, - ngg_get_emulated_counters_buf(ctx), - LLVMConstInt(ctx->ac.i32, - (si_hw_query_dw_offset(PIPE_STAT_QUERY_GS_PRIMITIVES) + - SI_QUERY_STATS_END_OFFSET_DW) * 4, - false), - ctx->ac.i32_0, /* soffset */ - ctx->ac.i32_0, /* cachepolicy */ - }; + if (ctx->screen->info.gfx_level < GFX11) { + tmp = si_unpack_param(ctx, ctx->vs_state_bits, 31, 1); + tmp = LLVMBuildTrunc(builder, tmp, ctx->ac.i1, ""); + ac_build_ifcc(&ctx->ac, tmp, 5229); /* if (GS_PIPELINE_STATS_EMU) */ + ac_build_ifcc(&ctx->ac, LLVMBuildNot(builder, prim.isnull, ""), 5237); + { + LLVMValueRef args[] = { + ctx->ac.i32_1, + ngg_get_emulated_counters_buf(ctx), + LLVMConstInt(ctx->ac.i32, + (si_hw_query_dw_offset(PIPE_STAT_QUERY_GS_PRIMITIVES) + + SI_QUERY_STATS_END_OFFSET_DW) * 4, + false), + ctx->ac.i32_0, /* soffset */ + ctx->ac.i32_0, /* cachepolicy */ + }; - ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.raw.buffer.atomic.add.i32", ctx->ac.i32, args, 5, 0); + ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.raw.buffer.atomic.add.i32", ctx->ac.i32, args, 5, 0); + } + ac_build_endif(&ctx->ac, 5237); + ac_build_endif(&ctx->ac, 5229); } - ac_build_endif(&ctx->ac, 5237); - ac_build_endif(&ctx->ac, 5229); } ac_build_endif(&ctx->ac, 5140);