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i965,anv: Set the CS stall bit on the ISP disable PIPE_CONTROL

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From the bspec docs for "Indirect State Pointers Disable":

    "At the completion of the post-sync operation associated with this
    pipe control packet, the indirect state pointers in the hardware are
    considered invalid"

So the ISP disable is a post-sync type of operation which means that it
should be combined with a CS stall.  Without this, the simulator throws
an error.

Fixes: 766d801ca "anv: emit pixel scoreboard stall before ISP disable"
Fixes: f536097f6 "i965: require pixel scoreboard stall prior to ISP disable"
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
This commit is contained in:
Jason Ekstrand 2018-05-09 15:06:13 -07:00
parent 56766b8515
commit a8a740f272
2 changed files with 3 additions and 1 deletions
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1
src/intel/vulkan/genX_cmd_buffer.c
View file

@ -1434,6 +1434,7 @@ emit_isp_disable(struct anv_cmd_buffer *cmd_buffer)
}
anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {
pc.IndirectStatePointersDisable = true;
pc.CommandStreamerStallEnable = true;
}
}

3
src/mesa/drivers/dri/i965/brw_pipe_control.c
View file

@ -362,7 +362,8 @@ gen10_emit_isp_disable(struct brw_context *brw)
PIPE_CONTROL_CS_STALL,
NULL, 0, 0);
brw_emit_pipe_control(brw,
PIPE_CONTROL_ISP_DIS,
PIPE_CONTROL_ISP_DIS |
PIPE_CONTROL_CS_STALL,
NULL, 0, 0);
brw->vs.base.push_constants_dirty = true;