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freedreno/registers: De-open-code some offsets

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Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37009>
This commit is contained in:
Rob Clark 2025-08-20 09:04:18 -07:00 • committed by Marge Bot
parent fd93414496
commit a84069cff4
2 changed files with 6 additions and 2 deletions
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5
src/freedreno/common/freedreno_devices.py
View file

@ -1350,8 +1350,9 @@ add_gpus([
[A6XXRegs.REG_A7XX_RB_UNKNOWN_8899, 0x00000000],
[A6XXRegs.REG_A7XX_RB_UNKNOWN_8C34, 0x00000000],
[0x930a, 0],
[0x960a, 1],
[A6XXRegs.REG_A7XX_VPC_UNKNOWN_930A, 0],
[A6XXRegs.REG_A7XX_PC_UNKNOWN_9EB6, 0],
[A6XXRegs.REG_A7XX_SP_PS_OUTPUT_CONST_CNTL, 0],
[A6XXRegs.REG_A7XX_SP_PS_OUTPUT_CONST_MASK, 0],
],

3
src/freedreno/registers/adreno/a6xx.xml
View file

@ -2186,6 +2186,9 @@ by a particular renderpass/blit.
<bitfield name="SIZE_GMEM" low="0" high="31"/>
</reg32>
<reg32 offset="0x930a" name="VPC_UNKNOWN_930A" variants="A7XX"/>
<reg32 offset="0x9eb6" name="PC_UNKNOWN_9EB6" variants="A7XX"/>
<!-- 0x9307-0x95ff invalid -->
<!-- TODO: 0x9600-0x97ff range -->