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anv: Add missing untyped data port flush on PIPELINE_SELECT

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See the comments in emit_apply_pipe_flushes().  Flushing HDC is not
sufficient in GPGPU mode, and we need to set the untyped data port flush
bit as well.

Fixes many dEQP-VK failures with INTEL_COMPUTE_CLASS=1 on Alchemist.

Fixes: 1067ec90a5 ("anv: Update PIPELINE_CONTROL flush when switching pipeline mode in TGL+")
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20774>
This commit is contained in:
Kenneth Graunke 2023-01-18 02:50:32 -08:00 • committed by Marge Bot
parent bc07b1a0bf
commit a8108f1d44
1 changed files with 2 additions and 0 deletions
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2
src/intel/vulkan/genX_cmd_buffer.c
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@ -6436,6 +6436,8 @@ genX(flush_pipeline_select)(struct anv_cmd_buffer *cmd_buffer,
if (cmd_buffer->state.current_pipeline == _3D) { if (cmd_buffer->state.current_pipeline == _3D) {
bits |= ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT | bits |= ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT |
ANV_PIPE_DEPTH_CACHE_FLUSH_BIT; ANV_PIPE_DEPTH_CACHE_FLUSH_BIT;
} else {
bits |= ANV_PIPE_UNTYPED_DATAPORT_CACHE_FLUSH_BIT;
} }
anv_add_pending_pipe_bits(cmd_buffer, bits, "flush PIPELINE_SELECT"); anv_add_pending_pipe_bits(cmd_buffer, bits, "flush PIPELINE_SELECT");
#else #else