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anv: Update PIPELINE_CONTROL flush when switching pipeline mode in TGL+

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This 2 PIPELINE_CONTROL flushes are not necessary for TGL and newer
and also it have different requirements of flush, so here doing
this two changes at the same time.

As no ANV_PIPE_INVALIDATE_BITS is set as parameter of
anv_add_pending_pipe_bits(),
genX(cmd_buffer_apply_pipe_flushes)(cmd_buffer) will only emit one
PIPELINE_CONTROL.

BSpec: 44505
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20501>
This commit is contained in:
José Roberto de Souza 2023-01-03 09:40:54 -08:00 • committed by Marge Bot
parent 172e0b0ebf
commit 1067ec90a5
1 changed files with 25 additions and 0 deletions
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25
src/intel/vulkan/genX_cmd_buffer.c
View file

@ -6347,6 +6347,30 @@ genX(flush_pipeline_select)(struct anv_cmd_buffer *cmd_buffer,
}
#endif
#if GFX_VER >= 12
/* From Tigerlake PRM, Volume 2a, PIPELINE_SELECT:
*
* "Software must ensure Render Cache, Depth Cache and HDC Pipeline flush
* are flushed through a stalling PIPE_CONTROL command prior to
* programming of PIPELINE_SELECT command transitioning Pipeline Select
* from 3D to GPGPU/Media.
* Software must ensure HDC Pipeline flush and Generic Media State Clear
* is issued through a stalling PIPE_CONTROL command prior to programming
* of PIPELINE_SELECT command transitioning Pipeline Select from
* GPGPU/Media to 3D."
*
* Note: Issuing PIPE_CONTROL_MEDIA_STATE_CLEAR causes GPU hangs, probably
* because PIPE was not in MEDIA mode?!
*/
enum anv_pipe_bits bits = ANV_PIPE_CS_STALL_BIT |
ANV_PIPE_HDC_PIPELINE_FLUSH_BIT;
if (cmd_buffer->state.current_pipeline == _3D) {
bits |= ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT |
ANV_PIPE_DEPTH_CACHE_FLUSH_BIT;
}
anv_add_pending_pipe_bits(cmd_buffer, bits, "flush PIPELINE_SELECT");
#else
/* From "BXML » GT » MI » vol1a GPU Overview » [Instruction]
* PIPELINE_SELECT [DevBWR+]":
*
@ -6371,6 +6395,7 @@ genX(flush_pipeline_select)(struct anv_cmd_buffer *cmd_buffer,
ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT |
ANV_PIPE_UNTYPED_DATAPORT_CACHE_FLUSH_BIT,
"flush and invalidate for PIPELINE_SELECT");
#endif
genX(cmd_buffer_apply_pipe_flushes)(cmd_buffer);
genX(emit_pipeline_select)(&cmd_buffer->batch, pipeline);