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jay/to_binary: rename grf -> phys_reg
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Browse source 
since it covers accumulators to

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41215>
This commit is contained in:
Alyssa Rosenzweig 2026-04-27 17:03:57 -04:00 • committed by Marge Bot
parent ab87a035c9
commit a78634ccb0
1 changed files with 8 additions and 8 deletions
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16
src/intel/compiler/jay/jay_to_binary.c
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@ -95,13 +95,13 @@ to_brw_reg(jay_function *f,
} else if (jay_is_null(d)) {
R = brw_null_reg();
} else if (d.file == UGPR || d.file == UACCUM) {
unsigned grf = (reg >> 1) / 8;
unsigned phys_reg = (reg >> 1) / 8;
offset_B = ((reg >> 1) % 8) * 4;
if (d.file == UGPR) {
R = brw_ud1_grf(grf, 0);
R = brw_ud1_grf(phys_reg, 0);
} else {
R = brw_ud1_reg(ARF, BRW_ARF_ACCUMULATOR + (grf * 2), 0);
R = brw_ud1_reg(ARF, BRW_ARF_ACCUMULATOR + (phys_reg * 2), 0);
}
/* Handle 3-src restrictions and vectorized uniform code. */
@ -140,23 +140,23 @@ to_brw_reg(jay_function *f,
unsigned stride_bits = jay_stride_to_bits(def_stride);
unsigned simd_width = jay_simd_width_physical(f->shader, I);
unsigned grf;
unsigned phys_reg;
if (def_stride == JAY_STRIDE_2) {
/* Bit 0 selects between lo/hi halves of the GPR */
grf = (reg / 2) * jay_grf_per_gpr(f->shader);
phys_reg = (reg / 2) * jay_grf_per_gpr(f->shader);
offset_B = (reg & 1) * 2 * f->shader->dispatch_width;
} else {
/* Low bits are an offset in 2-byte words into the GRF */
unsigned mask = BITFIELD_MASK(stride_bits / 32);
grf = ((reg & ~mask) / 2) * jay_grf_per_gpr(f->shader);
phys_reg = ((reg & ~mask) / 2) * jay_grf_per_gpr(f->shader);
offset_B = (reg & mask) * 2;
}
if (d.file == GPR) {
R = byte_offset(xe2_vec8_grf(grf, 0),
R = byte_offset(xe2_vec8_grf(phys_reg, 0),
simd_offs * simd_width * stride_bits / 8);
} else {
R = brw_vecn_reg(8, ARF, BRW_ARF_ACCUMULATOR + (grf * 2), 0);
R = brw_vecn_reg(8, ARF, BRW_ARF_ACCUMULATOR + (phys_reg * 2), 0);
}
if (stride_bits == (type_bits * 4)) {