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intel/brw/xe3+: Bump number of SBID tokens for Xe3.

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Xe3 supports 32 SBID tokens per thread regardless of the number of
register blocks allocated per thread.  Take advantage of the increased
number of SBIDs in the scoreboard pass to reduce the frequency of
false dependencies on Xe3+.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32664>
This commit is contained in:
Francisco Jerez 2024-09-18 14:26:54 -07:00 • committed by Marge Bot
parent 8d2331fe4b
commit a67ff3e7e3
1 changed files with 2 additions and 2 deletions
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4
src/intel/compiler/brw_lower_scoreboard.cpp
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@ -1232,9 +1232,9 @@ namespace {
/* XXX - Use bin-packing algorithm to assign hardware SBIDs optimally in
* shaders with a large number of SEND messages.
*
* XXX - Use 32 SBIDs on Xe2+ while in large GRF mode.
* XXX - Use 32 SBIDs on Xe2 while in large GRF mode.
*/
const unsigned num_sbids = 16;
const unsigned num_sbids = (shader->devinfo->ver >= 30 ? 32 : 16);
/* Allocate an unordered dependency ID to hardware SBID translation
* table with as many entries as instructions there are in the shader,