From a67ff3e7e3fc135012290cf0320b6434bb0e417b Mon Sep 17 00:00:00 2001 From: Francisco Jerez Date: Wed, 18 Sep 2024 14:26:54 -0700 Subject: [PATCH] intel/brw/xe3+: Bump number of SBID tokens for Xe3. Xe3 supports 32 SBID tokens per thread regardless of the number of register blocks allocated per thread. Take advantage of the increased number of SBIDs in the scoreboard pass to reduce the frequency of false dependencies on Xe3+. Reviewed-by: Lionel Landwerlin Part-of: --- src/intel/compiler/brw_lower_scoreboard.cpp | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/intel/compiler/brw_lower_scoreboard.cpp b/src/intel/compiler/brw_lower_scoreboard.cpp index f20f0655612..a54659336d8 100644 --- a/src/intel/compiler/brw_lower_scoreboard.cpp +++ b/src/intel/compiler/brw_lower_scoreboard.cpp @@ -1232,9 +1232,9 @@ namespace { /* XXX - Use bin-packing algorithm to assign hardware SBIDs optimally in * shaders with a large number of SEND messages. * - * XXX - Use 32 SBIDs on Xe2+ while in large GRF mode. + * XXX - Use 32 SBIDs on Xe2 while in large GRF mode. */ - const unsigned num_sbids = 16; + const unsigned num_sbids = (shader->devinfo->ver >= 30 ? 32 : 16); /* Allocate an unordered dependency ID to hardware SBID translation * table with as many entries as instructions there are in the shader,