From a676ba92941aa9bbef155c677a7db7536fa41a06 Mon Sep 17 00:00:00 2001 From: Sagar Ghuge Date: Tue, 17 Jun 2025 09:36:04 -0700 Subject: [PATCH] anv: Apply flush during WriteAccelerationStructures We are reading accel header parameter those are updated by CS, so we need to apply flushes to make L3 coherent with CS. This fixes ray query tests on MTL: - dEQP-VK.ray_query.*.serialization.* Cc: mesa-stable Signed-off-by: Sagar Ghuge Reviewed-by: Lionel Landwerlin Part-of: --- src/intel/vulkan/genX_query.c | 15 +++++++++++---- 1 file changed, 11 insertions(+), 4 deletions(-) diff --git a/src/intel/vulkan/genX_query.c b/src/intel/vulkan/genX_query.c index 8458213d078..83ac5ee7c27 100644 --- a/src/intel/vulkan/genX_query.c +++ b/src/intel/vulkan/genX_query.c @@ -2066,10 +2066,17 @@ genX(CmdWriteAccelerationStructuresPropertiesKHR)( ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer); ANV_FROM_HANDLE(anv_query_pool, pool, queryPool); - anv_add_pending_pipe_bits(cmd_buffer, - ANV_PIPE_END_OF_PIPE_SYNC_BIT | - ANV_PIPE_DATA_CACHE_FLUSH_BIT, - "read BVH data using CS"); + /* L1/L2 caches flushes should have been dealt with by pipeline barriers. + * Unfortunately some platforms require L3 flush because CS (reading the + * dispatch parameters) is not L3 coherent. + */ + if (!ANV_DEVINFO_HAS_COHERENT_L3_CS(cmd_buffer->device->info)) { + anv_add_pending_pipe_bits(cmd_buffer, + ANV_PIPE_END_OF_PIPE_SYNC_BIT | + ANV_PIPE_DATA_CACHE_FLUSH_BIT, + "read BVH data using CS"); + genX(cmd_buffer_apply_pipe_flushes)(cmd_buffer); + } if (append_query_clear_flush( cmd_buffer, pool,