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radv: fix emitting the border color pointer on the compute queue

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This was just missing.

Fixes: 57e796a12a ("radv: Implement VK_EXT_custom_border_color")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: John Galt <johngaltfirstrun@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6276>
(cherry picked from commit 638a09b827)
This commit is contained in:
Samuel Pitoiset 2020-08-11 10:00:42 +02:00 • committed by Dylan Baker
parent 11edf2e357
commit a4dc1baf77
4 changed files with 23 additions and 11 deletions
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2
.pick_status.json
View file

@ -301,7 +301,7 @@
"description": "radv: fix emitting the border color pointer on the compute queue",
"nominated": true,
"nomination_type": 1,
"resolution": 0,
"resolution": 1,
"master_sha": null,
"because_sha": "57e796a12a883f5845c8e0ed05ec6bdb6d055b53"
},

3
src/amd/vulkan/radv_device.c
View file

@ -3398,8 +3398,7 @@ radv_init_graphics_state(struct radeon_cmdbuf *cs, struct radv_queue *queue)
static void
radv_init_compute_state(struct radeon_cmdbuf *cs, struct radv_queue *queue)
{
struct radv_physical_device *physical_device = queue->device->physical_device;
si_emit_compute(physical_device, cs);
si_emit_compute(queue->device, cs);
}
static VkResult

2
src/amd/vulkan/radv_private.h
View file

@ -1416,7 +1416,7 @@ bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer *cmd_buffer);
void si_emit_graphics(struct radv_device *device,
struct radeon_cmdbuf *cs);
void si_emit_compute(struct radv_physical_device *physical_device,
void si_emit_compute(struct radv_device *device,
struct radeon_cmdbuf *cs);
void cik_create_gfx_config(struct radv_device *device);

27
src/amd/vulkan/si_cmd_buffer.c
View file

@ -78,7 +78,7 @@ si_write_harvested_raster_configs(struct radv_physical_device *physical_device,
}
void
si_emit_compute(struct radv_physical_device *physical_device,
si_emit_compute(struct radv_device *device,
struct radeon_cmdbuf *cs)
{
radeon_set_sh_reg_seq(cs, R_00B810_COMPUTE_START_X, 3);
@ -92,7 +92,7 @@ si_emit_compute(struct radv_physical_device *physical_device,
radeon_emit(cs, S_00B858_SH0_CU_EN(0xffff) | S_00B858_SH1_CU_EN(0xffff));
radeon_emit(cs, S_00B858_SH0_CU_EN(0xffff) | S_00B858_SH1_CU_EN(0xffff));
if (physical_device->rad_info.chip_class >= GFX7) {
if (device->physical_device->rad_info.chip_class >= GFX7) {
/* Also set R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE2 / SE3 */
radeon_set_sh_reg_seq(cs,
R_00B864_COMPUTE_STATIC_THREAD_MGMT_SE2, 2);
@ -100,14 +100,22 @@ si_emit_compute(struct radv_physical_device *physical_device,
S_00B858_SH1_CU_EN(0xffff));
radeon_emit(cs, S_00B858_SH0_CU_EN(0xffff) |
S_00B858_SH1_CU_EN(0xffff));
if (device->border_color_data.bo) {
uint64_t bc_va = radv_buffer_get_va(device->border_color_data.bo);
radeon_set_uconfig_reg_seq(cs, R_030E00_TA_CS_BC_BASE_ADDR, 2);
radeon_emit(cs, bc_va >> 8);
radeon_emit(cs, S_030E04_ADDRESS(bc_va >> 40));
}
}
if (physical_device->rad_info.chip_class >= GFX9) {
if (device->physical_device->rad_info.chip_class >= GFX9) {
radeon_set_uconfig_reg(cs, R_0301EC_CP_COHER_START_DELAY,
physical_device->rad_info.chip_class >= GFX10 ? 0x20 : 0);
device->physical_device->rad_info.chip_class >= GFX10 ? 0x20 : 0);
}
if (physical_device->rad_info.chip_class >= GFX10) {
if (device->physical_device->rad_info.chip_class >= GFX10) {
radeon_set_sh_reg(cs, R_00B890_COMPUTE_USER_ACCUM_0, 0);
radeon_set_sh_reg(cs, R_00B894_COMPUTE_USER_ACCUM_1, 0);
radeon_set_sh_reg(cs, R_00B898_COMPUTE_USER_ACCUM_2, 0);
@ -121,12 +129,17 @@ si_emit_compute(struct radv_physical_device *physical_device,
* kernel if we want to use something other than the default value,
* which is now 0x22f.
*/
if (physical_device->rad_info.chip_class <= GFX6) {
if (device->physical_device->rad_info.chip_class <= GFX6) {
/* XXX: This should be:
* (number of compute units) * 4 * (waves per simd) - 1 */
radeon_set_sh_reg(cs, R_00B82C_COMPUTE_MAX_WAVE_ID,
0x190 /* Default value */);
if (device->border_color_data.bo) {
uint64_t bc_va = radv_buffer_get_va(device->border_color_data.bo);
radeon_set_config_reg(cs, R_00950C_TA_CS_BC_BASE_ADDR, bc_va >> 8);
}
}
}
@ -559,7 +572,7 @@ si_emit_graphics(struct radv_device *device,
S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
si_emit_compute(physical_device, cs);
si_emit_compute(device, cs);
}
void