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intel/isl: Align non-tiled horizontally by cache line

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in order to support blit engine.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
This commit is contained in:
Topi Pohjolainen 2017-06-28 12:07:32 +03:00
parent 75f95c710f
commit a40f043034
1 changed files with 15 additions and 1 deletions
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16
src/intel/isl/isl.c
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@ -1268,9 +1268,23 @@ isl_calc_row_pitch(const struct isl_device *dev,
const struct isl_extent2d *phys_total_el,
uint32_t *out_row_pitch)
{
const uint32_t alignment =
uint32_t alignment =
isl_calc_row_pitch_alignment(surf_info, tile_info);
/* If pitch isn't given and it can be chosen freely, align it by cache line
* allowing one to use blit engine on the surface.
*/
if (surf_info->row_pitch == 0 && tile_info->tiling == ISL_TILING_LINEAR) {
/* From the Broadwell PRM docs for XY_SRC_COPY_BLT::SourceBaseAddress:
*
* "Base address of the destination surface: X=0, Y=0. Lower 32bits
* of the 48bit addressing. When Src Tiling is enabled (Bit_15
* enabled), this address must be 4KB-aligned. When Tiling is not
* enabled, this address should be CL (64byte) aligned."
*/
alignment = MAX2(alignment, 64);
}
const uint32_t min_row_pitch =
isl_calc_min_row_pitch(dev, surf_info, tile_info, phys_total_el,
alignment);