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i965/miptree/gen4: Prepare x-tiled fallback for isl based

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Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
This commit is contained in:
Topi Pohjolainen 2017-06-20 20:33:08 +03:00
parent 4ea63fab77
commit 75f95c710f
1 changed files with 20 additions and 6 deletions
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26
src/mesa/drivers/dri/i965/intel_mipmap_tree.c
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@ -742,6 +742,21 @@ need_to_retile_as_linear(struct brw_context *brw, unsigned row_pitch,
return false;
}
static bool
need_to_retile_as_x(const struct brw_context *brw, uint64_t size,
enum isl_tiling tiling)
{
/* If the BO is too large to fit in the aperture, we need to use the
* BLT engine to support it. Prior to Sandybridge, the BLT paths can't
* handle Y-tiling, so we need to fall back to X.
*/
if (brw->gen < 6 && size >= brw->max_gtt_map_object_size &&
tiling == ISL_TILING_Y0)
return true;
return false;
}
static struct intel_mipmap_tree *
make_surface(struct brw_context *brw, GLenum target, mesa_format format,
unsigned first_level, unsigned last_level,
@ -800,6 +815,10 @@ make_surface(struct brw_context *brw, GLenum target, mesa_format format,
init_info.tiling_flags = 1u << ISL_TILING_LINEAR;
if (!isl_surf_init_s(&brw->isl_dev, &mt->surf, &init_info))
goto fail;
} else if (need_to_retile_as_x(brw, mt->surf.size, mt->surf.tiling)) {
init_info.tiling_flags = 1u << ISL_TILING_X;
if (!isl_surf_init_s(&brw->isl_dev, &mt->surf, &init_info))
goto fail;
}
}
@ -1000,12 +1019,7 @@ intel_miptree_create(struct brw_context *brw,
if (!mt)
return NULL;
/* If the BO is too large to fit in the aperture, we need to use the
* BLT engine to support it. Prior to Sandybridge, the BLT paths can't
* handle Y-tiling, so we need to fall back to X.
*/
if (brw->gen < 6 && mt->bo->size >= brw->max_gtt_map_object_size &&
mt->surf.tiling == ISL_TILING_Y0) {
if (need_to_retile_as_x(brw, mt->bo->size, mt->surf.tiling)) {
const uint32_t alloc_flags =
(layout_flags & MIPTREE_LAYOUT_ACCELERATED_UPLOAD) ?
BO_ALLOC_FOR_RENDER : 0;