From a2c2a7bc0045010edf26cbe8b375561d0aba14b8 Mon Sep 17 00:00:00 2001 From: Kenneth Graunke Date: Thu, 21 Mar 2024 10:58:20 -0700 Subject: [PATCH] intel/brw: Fix check for 64-bit SEL lowering types The 64-bit type lowering for SEL in opt_algebraic had a pre-existing bug where it only triggered when 64-bit float _and_ integer types were unsupported. Meteorlake supports 64-bit float but not integer, so we need to lower Q/UQ in that case still. When I moved this to a later pass, opt_peephole_sel started generating Q/UQ SEL instructions which were failing to be lowered. Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/10867 Fixes: ea423aba1b45 ("intel/brw: Split out 64-bit lowering from algebraic optimizations") Reviewed-by: Lionel Landwerlin Part-of: --- src/intel/compiler/brw_fs_lower.cpp | 15 ++++++++++----- 1 file changed, 10 insertions(+), 5 deletions(-) diff --git a/src/intel/compiler/brw_fs_lower.cpp b/src/intel/compiler/brw_fs_lower.cpp index c8ce381aa31..eda5ec70663 100644 --- a/src/intel/compiler/brw_fs_lower.cpp +++ b/src/intel/compiler/brw_fs_lower.cpp @@ -562,6 +562,15 @@ brw_fs_lower_3src_null_dest(fs_visitor &s) return progress; } +static bool +unsupported_64bit_type(const intel_device_info *devinfo, + enum brw_reg_type type) +{ + return (!devinfo->has_64bit_float && type == BRW_REGISTER_TYPE_DF) || + (!devinfo->has_64bit_int && (type == BRW_REGISTER_TYPE_UQ || + type == BRW_REGISTER_TYPE_Q)); +} + /** * Perform lowering to legalize the IR for various ALU restrictions. * @@ -620,11 +629,7 @@ brw_fs_lower_alu_restrictions(fs_visitor &s) break; case BRW_OPCODE_SEL: - if (!devinfo->has_64bit_float && - !devinfo->has_64bit_int && - (inst->dst.type == BRW_REGISTER_TYPE_DF || - inst->dst.type == BRW_REGISTER_TYPE_UQ || - inst->dst.type == BRW_REGISTER_TYPE_Q)) { + if (unsupported_64bit_type(devinfo, inst->dst.type)) { assert(inst->dst.type == inst->src[0].type); assert(!inst->saturate); assert(!inst->src[0].abs && !inst->src[0].negate);