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freedreno/a6xx: Add RB_DBG_ECO_MODE helper

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Avoid sprinkling the logic for blit vs non-blit values everywhere.

Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38450>
This commit is contained in:
Rob Clark 2025-10-23 09:25:45 -07:00 • committed by Marge Bot
parent 56015d8cd9
commit a24f3efd98
3 changed files with 25 additions and 29 deletions
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14
src/gallium/drivers/freedreno/a6xx/fd6_blitter.cc
View file

@ -275,24 +275,14 @@ template <chip CHIP>
static void static void
emit_blit_fini(struct fd_context *ctx, fd_cs &cs) emit_blit_fini(struct fd_context *ctx, fd_cs &cs)
{ {
const struct fd_dev_info *info = ctx->screen->info;
fd6_event_write<CHIP>(ctx, cs, FD_LABEL); fd6_event_write<CHIP>(ctx, cs, FD_LABEL);
if (info->magic.RB_DBG_ECO_CNTL != info->magic.RB_DBG_ECO_CNTL_blit) { fd6_set_rb_dbg_eco_mode<CHIP>(ctx, cs, true);
fd_pkt7(cs, CP_WAIT_FOR_IDLE, 0);
fd_pkt4(cs, 1)
.add(A6XX_RB_DBG_ECO_CNTL(.dword = info->magic.RB_DBG_ECO_CNTL_blit));
}
fd_pkt7(cs, CP_BLIT, 1) fd_pkt7(cs, CP_BLIT, 1)
.add(CP_BLIT_0(.op = BLIT_OP_SCALE)); .add(CP_BLIT_0(.op = BLIT_OP_SCALE));
if (info->magic.RB_DBG_ECO_CNTL != info->magic.RB_DBG_ECO_CNTL_blit) { fd6_set_rb_dbg_eco_mode<CHIP>(ctx, cs, false);
fd_pkt7(cs, CP_WAIT_FOR_IDLE, 0);
fd_pkt4(cs, 1)
.add(A6XX_RB_DBG_ECO_CNTL(.dword = info->magic.RB_DBG_ECO_CNTL));
}
} }
/* nregs: 5 */ /* nregs: 5 */

21
src/gallium/drivers/freedreno/a6xx/fd6_emit.h
View file

@ -290,6 +290,27 @@ fd6_emit_blit(struct fd_context *ctx, fd_cs &cs)
emit_marker6<CHIP>(cs, 7); emit_marker6<CHIP>(cs, 7);
} }
template <chip CHIP>
static inline void
fd6_set_rb_dbg_eco_mode(struct fd_context *ctx, fd_cs &cs, bool blit)
{
/* Later things do not make this accessible to UMD: */
if (CHIP >= A7XX)
return;
const struct fd_dev_info *info = ctx->screen->info;
if (info->magic.RB_DBG_ECO_CNTL == info->magic.RB_DBG_ECO_CNTL_blit)
return;
uint32_t dword = blit ? info->magic.RB_DBG_ECO_CNTL_blit :
info->magic.RB_DBG_ECO_CNTL;
fd_pkt7(cs, CP_WAIT_FOR_IDLE, 0);
fd_pkt4(cs, 1)
.add(A6XX_RB_DBG_ECO_CNTL(.dword = dword));
}
static inline bool static inline bool
fd6_geom_stage(mesa_shader_stage type) fd6_geom_stage(mesa_shader_stage type)
{ {

19
src/gallium/drivers/freedreno/a6xx/fd6_gmem.cc
View file

@ -305,15 +305,7 @@ emit_lrz_clears(struct fd_batch *batch)
fd6_emit_flushes<CHIP>(ctx, cs, FD6_FLUSH_CACHE); fd6_emit_flushes<CHIP>(ctx, cs, FD6_FLUSH_CACHE);
if (ctx->screen->info->magic.RB_DBG_ECO_CNTL_blit != fd6_set_rb_dbg_eco_mode<CHIP>(ctx, cs, true);
ctx->screen->info->magic.RB_DBG_ECO_CNTL) {
/* This a non-context register, so we have to WFI before changing. */
fd_pkt7(cs, CP_WAIT_FOR_IDLE, 0);
fd_pkt4(cs, 1)
.add(A6XX_RB_DBG_ECO_CNTL(
.dword = ctx->screen->info->magic.RB_DBG_ECO_CNTL_blit
));
}
} }
fd6_clear_lrz<CHIP>(batch, zsbuf, subpass->lrz, subpass->clear_depth); fd6_clear_lrz<CHIP>(batch, zsbuf, subpass->lrz, subpass->clear_depth);
@ -325,14 +317,7 @@ emit_lrz_clears(struct fd_batch *batch)
if (count > 0) { if (count > 0) {
fd_cs cs(fd_batch_get_prologue(batch)); fd_cs cs(fd_batch_get_prologue(batch));
if (ctx->screen->info->magic.RB_DBG_ECO_CNTL_blit != fd6_set_rb_dbg_eco_mode<CHIP>(ctx, cs, false);
ctx->screen->info->magic.RB_DBG_ECO_CNTL) {
fd_pkt7(cs, CP_WAIT_FOR_IDLE, 0);
fd_pkt4(cs, 1)
.add(A6XX_RB_DBG_ECO_CNTL(
.dword = ctx->screen->info->magic.RB_DBG_ECO_CNTL
));
}
/* Clearing writes via CCU color in the PS stage, and LRZ is read via /* Clearing writes via CCU color in the PS stage, and LRZ is read via
* UCHE in the earlier GRAS stage. * UCHE in the earlier GRAS stage.