diff --git a/src/gallium/drivers/freedreno/a6xx/fd6_blitter.cc b/src/gallium/drivers/freedreno/a6xx/fd6_blitter.cc
index 8b26311f34a..1f630524ab1 100644
--- a/src/gallium/drivers/freedreno/a6xx/fd6_blitter.cc
+++ b/src/gallium/drivers/freedreno/a6xx/fd6_blitter.cc
@@ -275,24 +275,14 @@ template <chip CHIP>
 static void
 emit_blit_fini(struct fd_context *ctx, fd_cs &cs)
 {
-   const struct fd_dev_info *info = ctx->screen->info;
-
    fd6_event_write<CHIP>(ctx, cs, FD_LABEL);
 
-   if (info->magic.RB_DBG_ECO_CNTL != info->magic.RB_DBG_ECO_CNTL_blit) {
-      fd_pkt7(cs, CP_WAIT_FOR_IDLE, 0);
-      fd_pkt4(cs, 1)
-         .add(A6XX_RB_DBG_ECO_CNTL(.dword = info->magic.RB_DBG_ECO_CNTL_blit));
-   }
+   fd6_set_rb_dbg_eco_mode<CHIP>(ctx, cs, true);
 
    fd_pkt7(cs, CP_BLIT, 1)
       .add(CP_BLIT_0(.op = BLIT_OP_SCALE));
 
-   if (info->magic.RB_DBG_ECO_CNTL != info->magic.RB_DBG_ECO_CNTL_blit) {
-      fd_pkt7(cs, CP_WAIT_FOR_IDLE, 0);
-      fd_pkt4(cs, 1)
-         .add(A6XX_RB_DBG_ECO_CNTL(.dword = info->magic.RB_DBG_ECO_CNTL));
-   }
+   fd6_set_rb_dbg_eco_mode<CHIP>(ctx, cs, false);
 }
 
 /* nregs: 5 */
diff --git a/src/gallium/drivers/freedreno/a6xx/fd6_emit.h b/src/gallium/drivers/freedreno/a6xx/fd6_emit.h
index 6000a985428..3e23f1d8f64 100644
--- a/src/gallium/drivers/freedreno/a6xx/fd6_emit.h
+++ b/src/gallium/drivers/freedreno/a6xx/fd6_emit.h
@@ -290,6 +290,27 @@ fd6_emit_blit(struct fd_context *ctx, fd_cs &cs)
    emit_marker6<CHIP>(cs, 7);
 }
 
+template <chip CHIP>
+static inline void
+fd6_set_rb_dbg_eco_mode(struct fd_context *ctx, fd_cs &cs, bool blit)
+{
+   /* Later things do not make this accessible to UMD: */
+   if (CHIP >= A7XX)
+      return;
+
+   const struct fd_dev_info *info = ctx->screen->info;
+
+   if (info->magic.RB_DBG_ECO_CNTL == info->magic.RB_DBG_ECO_CNTL_blit)
+      return;
+
+   uint32_t dword = blit ? info->magic.RB_DBG_ECO_CNTL_blit :
+                           info->magic.RB_DBG_ECO_CNTL;
+
+   fd_pkt7(cs, CP_WAIT_FOR_IDLE, 0);
+   fd_pkt4(cs, 1)
+      .add(A6XX_RB_DBG_ECO_CNTL(.dword = dword));
+}
+
 static inline bool
 fd6_geom_stage(mesa_shader_stage type)
 {
diff --git a/src/gallium/drivers/freedreno/a6xx/fd6_gmem.cc b/src/gallium/drivers/freedreno/a6xx/fd6_gmem.cc
index 30da374ae70..54648377d21 100644
--- a/src/gallium/drivers/freedreno/a6xx/fd6_gmem.cc
+++ b/src/gallium/drivers/freedreno/a6xx/fd6_gmem.cc
@@ -305,15 +305,7 @@ emit_lrz_clears(struct fd_batch *batch)
 
          fd6_emit_flushes<CHIP>(ctx, cs, FD6_FLUSH_CACHE);
 
-         if (ctx->screen->info->magic.RB_DBG_ECO_CNTL_blit !=
-             ctx->screen->info->magic.RB_DBG_ECO_CNTL) {
-            /* This a non-context register, so we have to WFI before changing. */
-            fd_pkt7(cs, CP_WAIT_FOR_IDLE, 0);
-            fd_pkt4(cs, 1)
-               .add(A6XX_RB_DBG_ECO_CNTL(
-                  .dword = ctx->screen->info->magic.RB_DBG_ECO_CNTL_blit
-               ));
-         }
+         fd6_set_rb_dbg_eco_mode<CHIP>(ctx, cs, true);
       }
 
       fd6_clear_lrz<CHIP>(batch, zsbuf, subpass->lrz, subpass->clear_depth);
@@ -325,14 +317,7 @@ emit_lrz_clears(struct fd_batch *batch)
    if (count > 0) {
       fd_cs cs(fd_batch_get_prologue(batch));
 
-      if (ctx->screen->info->magic.RB_DBG_ECO_CNTL_blit !=
-          ctx->screen->info->magic.RB_DBG_ECO_CNTL) {
-         fd_pkt7(cs, CP_WAIT_FOR_IDLE, 0);
-         fd_pkt4(cs, 1)
-            .add(A6XX_RB_DBG_ECO_CNTL(
-               .dword = ctx->screen->info->magic.RB_DBG_ECO_CNTL
-            ));
-      }
+      fd6_set_rb_dbg_eco_mode<CHIP>(ctx, cs, false);
 
       /* Clearing writes via CCU color in the PS stage, and LRZ is read via
        * UCHE in the earlier GRAS stage.