From a0fe068d9e414498074817acbb90e030509437a4 Mon Sep 17 00:00:00 2001 From: Rhys Perry Date: Mon, 1 Feb 2021 15:01:57 +0000 Subject: [PATCH] radv: correctly enable WGP_MODE for NGG and GS Previously, we would set WGP_MODE on GFX10+ and then only on GFX10. Because we used bitwise or, the result was WGP_MODE being set on GFX10+. We also set the wrong bit, S_00B848_WGP_MODE instead of S_00B228_WGP_MODE. Signed-off-by: Rhys Perry Reviewed-by: Samuel Pitoiset Cc: mesa-stable Part-of: (cherry picked from commit 2338e4ad36fc41414e0d2362e5191d39d218a1d4) --- .pick_status.json | 2 +- src/amd/vulkan/radv_shader.c | 8 ++++---- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/.pick_status.json b/.pick_status.json index 6bc6616f220..30016990b05 100644 --- a/.pick_status.json +++ b/.pick_status.json @@ -256,7 +256,7 @@ "description": "radv: correctly enable WGP_MODE for NGG and GS", "nominated": true, "nomination_type": 0, - "resolution": 0, + "resolution": 1, "master_sha": null, "because_sha": null }, diff --git a/src/amd/vulkan/radv_shader.c b/src/amd/vulkan/radv_shader.c index cf46223168e..9fd0f1ba853 100644 --- a/src/amd/vulkan/radv_shader.c +++ b/src/amd/vulkan/radv_shader.c @@ -1029,8 +1029,7 @@ static void radv_postprocess_config(const struct radv_device *device, S_00B02C_EXCP_EN(excp_en); break; case MESA_SHADER_GEOMETRY: - config_out->rsrc1 |= S_00B228_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10) | - S_00B848_WGP_MODE(pdevice->rad_info.chip_class >= GFX10); + config_out->rsrc1 |= S_00B228_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10); config_out->rsrc2 |= S_00B22C_SHARED_VGPR_CNT(num_shared_vgpr_blocks) | S_00B22C_EXCP_EN(excp_en); break; @@ -1087,7 +1086,7 @@ static void radv_postprocess_config(const struct radv_device *device, * disable exactly 1 CU per SA for GS. */ config_out->rsrc1 |= S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt) | - S_00B848_WGP_MODE(pdevice->rad_info.chip_class == GFX10); + S_00B228_WGP_MODE(pdevice->rad_info.chip_class == GFX10); config_out->rsrc2 |= S_00B22C_ES_VGPR_COMP_CNT(es_vgpr_comp_cnt) | S_00B22C_LDS_SIZE(config_in->lds_size) | S_00B22C_OC_LDS_EN(es_stage == MESA_SHADER_TESS_EVAL); @@ -1122,7 +1121,8 @@ static void radv_postprocess_config(const struct radv_device *device, gs_vgpr_comp_cnt = 0; /* VGPR0 contains offsets 0, 1 */ } - config_out->rsrc1 |= S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt); + config_out->rsrc1 |= S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt) | + S_00B228_WGP_MODE(pdevice->rad_info.chip_class >= GFX10); config_out->rsrc2 |= S_00B22C_ES_VGPR_COMP_CNT(es_vgpr_comp_cnt) | S_00B22C_OC_LDS_EN(es_type == MESA_SHADER_TESS_EVAL); } else if (pdevice->rad_info.chip_class >= GFX9 &&